projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 2ceb3fb0 AC |
1 | What: /sys/devices/system/cpu/ |
| 2 | Date: pre-git history | |
| 3 | Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org> | |
| 4 | Description: | |
| 5 | A collection of both global and individual CPU attributes | |
| 6 | ||
| 7 | Individual CPU attributes are contained in subdirectories | |
| 8 | named by the kernel's logical CPU number, e.g.: | |
| 9 | ||
| 10 | /sys/devices/system/cpu/cpu#/ | |
| 11 | ||
| 12 | ||
| 2fad2d9b ML |
13 | What: /sys/devices/system/cpu/cpu*/cache/index*/cache_disable_X |
| 14 | Date: August 2008 | |
| 15 | KernelVersion: 2.6.27 | |
| 16 | Contact: mark.langsdorf@amd.com | |
| 17 | Description: These files exist in every cpu's cache index directories. | |
| 18 | There are currently 2 cache_disable_# files in each | |
| 19 | directory. Reading from these files on a supported | |
| 20 | processor will return that cache disable index value | |
| 21 | for that processor and node. Writing to one of these | |
| 22 | files will cause the specificed cache index to be disabled. | |
| 23 | ||
| 24 | Currently, only AMD Family 10h Processors support cache index | |
| 25 | disable, and only for their L3 caches. See the BIOS and | |
| 26 | Kernel Developer's Guide at | |
| 27 | http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116-Public-GH-BKDG_3.20_2-4-09.pdf | |
| 28 | for formatting information and other details on the | |
| 29 | cache index disable. | |
| 30 | Users: joachim.deguara@amd.com |