[deliverable/linux.git] / Documentation / DMA-attributes.txt

			DMA attributes
			==============

This document describes the semantics of the DMA attributes that are
defined in linux/dma-attrs.h.

DMA_ATTR_WRITE_BARRIER
----------------------

DMA_ATTR_WRITE_BARRIER is a (write) barrier attribute for DMA.  DMA
to a memory region with the DMA_ATTR_WRITE_BARRIER attribute forces
all pending DMA writes to complete, and thus provides a mechanism to
strictly order DMA from a device across all intervening busses and
bridges.  This barrier is not specific to a particular type of
interconnect, it applies to the system as a whole, and so its
implementation must account for the idiosyncracies of the system all
the way from the DMA device to memory.

As an example of a situation where DMA_ATTR_WRITE_BARRIER would be
useful, suppose that a device does a DMA write to indicate that data is
ready and available in memory.  The DMA of the "completion indication"
could race with data DMA.  Mapping the memory used for completion
indications with DMA_ATTR_WRITE_BARRIER would prevent the race.

DMA_ATTR_WEAK_ORDERING
----------------------

DMA_ATTR_WEAK_ORDERING specifies that reads and writes to the mapping
may be weakly ordered, that is that reads and writes may pass each other.

Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING,
those that do not will simply ignore the attribute and exhibit default
behavior.
Commit	Line	Data
a75b0a2f AK	1	DMA attributes
	2	==============
	3
	4	This document describes the semantics of the DMA attributes that are
	5	defined in linux/dma-attrs.h.
	6
	7	DMA_ATTR_WRITE_BARRIER
	8	----------------------
	9
	10	DMA_ATTR_WRITE_BARRIER is a (write) barrier attribute for DMA. DMA
	11	to a memory region with the DMA_ATTR_WRITE_BARRIER attribute forces
	12	all pending DMA writes to complete, and thus provides a mechanism to
	13	strictly order DMA from a device across all intervening busses and
	14	bridges. This barrier is not specific to a particular type of
	15	interconnect, it applies to the system as a whole, and so its
	16	implementation must account for the idiosyncracies of the system all
	17	the way from the DMA device to memory.
	18
	19	As an example of a situation where DMA_ATTR_WRITE_BARRIER would be
	20	useful, suppose that a device does a DMA write to indicate that data is
	21	ready and available in memory. The DMA of the "completion indication"
	22	could race with data DMA. Mapping the memory used for completion
	23	indications with DMA_ATTR_WRITE_BARRIER would prevent the race.
	24
1ed6af73 MN	25	DMA_ATTR_WEAK_ORDERING
	26	----------------------
	27
	28	DMA_ATTR_WEAK_ORDERING specifies that reads and writes to the mapping
	29	may be weakly ordered, that is that reads and writes may pass each other.
	30
	31	Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING,
	32	those that do not will simply ignore the attribute and exhibit default
	33	behavior.