[deliverable/linux.git] / Documentation / arm / Samsung-S3C24XX / DMA.txt

			S3C2410 DMA
			===========

Introduction
------------

   The kernel provides an interface to manage DMA transfers
   using the DMA channels in the CPU, so that the central
   duty of managing channel mappings, and programming the
   channel generators is in one place.


DMA Channel Ordering
--------------------

   Many of the range do not have connections for the DMA
   channels to all sources, which means that some devices
   have a restricted number of channels that can be used.

   To allow flexibility for each CPU type and board, the
   DMA code can be given a DMA ordering structure which
   allows the order of channel search to be specified, as
   well as allowing the prohibition of certain claims.

   struct s3c24xx_dma_order has a list of channels, and
   each channel within has a slot for a list of DMA
   channel numbers. The slots are searched in order for
   the presence of a DMA channel number with DMA_CH_VALID
   or-ed in.

   If the order has the flag DMA_CH_NEVER set, then after
   checking the channel list, the system will return no
   found channel, thus denying the request.

   A board support file can call s3c24xx_dma_order_set()
   to register a complete ordering set. The routine will
   copy the data, so the original can be discarded with
   __initdata.


Authour
-------

Ben Dooks,
Copyright (c) 2007 Ben Dooks, Simtec Electronics
Licensed under the GPL v2
Commit	Line	Data
0c6022d4 BD	1	S3C2410 DMA
	2	===========
	3
	4	Introduction
	5	------------
	6
	7	The kernel provides an interface to manage DMA transfers
01dd2fbf	8	using the DMA channels in the CPU, so that the central
0c6022d4 BD	9	duty of managing channel mappings, and programming the
	10	channel generators is in one place.
	11
	12
	13	DMA Channel Ordering
	14	--------------------
	15
	16	Many of the range do not have connections for the DMA
	17	channels to all sources, which means that some devices
	18	have a restricted number of channels that can be used.
	19
01dd2fbf ML	20	To allow flexibility for each CPU type and board, the
01dd2fbf ML	21	DMA code can be given a DMA ordering structure which
0c6022d4 BD	22	allows the order of channel search to be specified, as
	23	well as allowing the prohibition of certain claims.
	24
	25	struct s3c24xx_dma_order has a list of channels, and
01dd2fbf ML	26	each channel within has a slot for a list of DMA
	27	channel numbers. The slots are searched in order for
	28	the presence of a DMA channel number with DMA_CH_VALID
	29	or-ed in.
0c6022d4 BD	30
	31	If the order has the flag DMA_CH_NEVER set, then after
	32	checking the channel list, the system will return no
	33	found channel, thus denying the request.
	34
	35	A board support file can call s3c24xx_dma_order_set()
01dd2fbf ML	36	to register a complete ordering set. The routine will
01dd2fbf ML	37	copy the data, so the original can be discarded with
0c6022d4 BD	38	__initdata.
	39
	40
	41	Authour
	42	-------
	43
	44	Ben Dooks,
	45	Copyright (c) 2007 Ben Dooks, Simtec Electronics
	46	Licensed under the GPL v2