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799656de MP |
1 | * CoreSight Components: |
2 | ||
3 | CoreSight components are compliant with the ARM CoreSight architecture | |
4 | specification and can be connected in various topologies to suit a particular | |
5 | SoCs tracing needs. These trace components can generally be classified as | |
6 | sinks, links and sources. Trace data produced by one or more sources flows | |
7 | through the intermediate links connecting the source to the currently selected | |
8 | sink. Each CoreSight component device should use these properties to describe | |
9 | its hardware characteristcs. | |
10 | ||
11 | * Required properties for all components *except* non-configurable replicators: | |
12 | ||
13 | * compatible: These have to be supplemented with "arm,primecell" as | |
14 | drivers are using the AMBA bus interface. Possible values include: | |
15 | - "arm,coresight-etb10", "arm,primecell"; | |
16 | - "arm,coresight-tpiu", "arm,primecell"; | |
17 | - "arm,coresight-tmc", "arm,primecell"; | |
18 | - "arm,coresight-funnel", "arm,primecell"; | |
19 | - "arm,coresight-etm3x", "arm,primecell"; | |
e5742ef1 | 20 | - "arm,coresight-etm4x", "arm,primecell"; |
620cf787 | 21 | - "qcom,coresight-replicator1x", "arm,primecell"; |
9eb93313 | 22 | - "arm,coresight-stm", "arm,primecell"; [1] |
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23 | |
24 | * reg: physical base address and length of the register | |
25 | set(s) of the component. | |
26 | ||
70dd9d2f LW |
27 | * clocks: the clocks associated to this component. |
28 | ||
29 | * clock-names: the name of the clocks referenced by the code. | |
30 | Since we are using the AMBA framework, the name of the clock | |
31 | providing the interconnect should be "apb_pclk", and some | |
32 | coresight blocks also have an additional clock "atclk", which | |
33 | clocks the core of that coresight component. The latter clock | |
34 | is optional. | |
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35 | |
36 | * port or ports: The representation of the component's port | |
37 | layout using the generic DT graph presentation found in | |
38 | "bindings/graph.txt". | |
39 | ||
9eb93313 MP |
40 | * Additional required properties for System Trace Macrocells (STM): |
41 | * reg: along with the physical base address and length of the register | |
42 | set as described above, another entry is required to describe the | |
43 | mapping of the extended stimulus port area. | |
44 | ||
45 | * reg-names: the only acceptable values are "stm-base" and | |
46 | "stm-stimulus-base", each corresponding to the areas defined in "reg". | |
47 | ||
799656de MP |
48 | * Required properties for devices that don't show up on the AMBA bus, such as |
49 | non-configurable replicators: | |
50 | ||
51 | * compatible: Currently supported value is (note the absence of the | |
52 | AMBA markee): | |
53 | - "arm,coresight-replicator" | |
54 | ||
799656de MP |
55 | * port or ports: same as above. |
56 | ||
57 | * Optional properties for ETM/PTMs: | |
58 | ||
59 | * arm,cp14: must be present if the system accesses ETM/PTM management | |
60 | registers via co-processor 14. | |
61 | ||
62 | * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the | |
63 | source is considered to belong to CPU0. | |
64 | ||
65 | * Optional property for TMC: | |
66 | ||
67 | * arm,buffer-size: size of contiguous buffer space for TMC ETR | |
68 | (embedded trace router) | |
69 | ||
70 | ||
71 | Example: | |
72 | ||
73 | 1. Sinks | |
74 | etb@20010000 { | |
75 | compatible = "arm,coresight-etb10", "arm,primecell"; | |
76 | reg = <0 0x20010000 0 0x1000>; | |
77 | ||
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78 | clocks = <&oscclk6a>; |
79 | clock-names = "apb_pclk"; | |
80 | port { | |
81 | etb_in_port: endpoint@0 { | |
82 | slave-mode; | |
83 | remote-endpoint = <&replicator_out_port0>; | |
84 | }; | |
85 | }; | |
86 | }; | |
87 | ||
88 | tpiu@20030000 { | |
89 | compatible = "arm,coresight-tpiu", "arm,primecell"; | |
90 | reg = <0 0x20030000 0 0x1000>; | |
91 | ||
92 | clocks = <&oscclk6a>; | |
93 | clock-names = "apb_pclk"; | |
94 | port { | |
95 | tpiu_in_port: endpoint@0 { | |
96 | slave-mode; | |
97 | remote-endpoint = <&replicator_out_port1>; | |
98 | }; | |
99 | }; | |
100 | }; | |
101 | ||
102 | 2. Links | |
103 | replicator { | |
104 | /* non-configurable replicators don't show up on the | |
105 | * AMBA bus. As such no need to add "arm,primecell". | |
106 | */ | |
107 | compatible = "arm,coresight-replicator"; | |
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108 | |
109 | ports { | |
110 | #address-cells = <1>; | |
111 | #size-cells = <0>; | |
112 | ||
113 | /* replicator output ports */ | |
114 | port@0 { | |
115 | reg = <0>; | |
116 | replicator_out_port0: endpoint { | |
117 | remote-endpoint = <&etb_in_port>; | |
118 | }; | |
119 | }; | |
120 | ||
121 | port@1 { | |
122 | reg = <1>; | |
123 | replicator_out_port1: endpoint { | |
124 | remote-endpoint = <&tpiu_in_port>; | |
125 | }; | |
126 | }; | |
127 | ||
128 | /* replicator input port */ | |
129 | port@2 { | |
130 | reg = <0>; | |
131 | replicator_in_port0: endpoint { | |
132 | slave-mode; | |
133 | remote-endpoint = <&funnel_out_port0>; | |
134 | }; | |
135 | }; | |
136 | }; | |
137 | }; | |
138 | ||
139 | funnel@20040000 { | |
140 | compatible = "arm,coresight-funnel", "arm,primecell"; | |
141 | reg = <0 0x20040000 0 0x1000>; | |
142 | ||
143 | clocks = <&oscclk6a>; | |
144 | clock-names = "apb_pclk"; | |
145 | ports { | |
146 | #address-cells = <1>; | |
147 | #size-cells = <0>; | |
148 | ||
149 | /* funnel output port */ | |
150 | port@0 { | |
151 | reg = <0>; | |
152 | funnel_out_port0: endpoint { | |
153 | remote-endpoint = | |
154 | <&replicator_in_port0>; | |
155 | }; | |
156 | }; | |
157 | ||
158 | /* funnel input ports */ | |
159 | port@1 { | |
160 | reg = <0>; | |
161 | funnel_in_port0: endpoint { | |
162 | slave-mode; | |
163 | remote-endpoint = <&ptm0_out_port>; | |
164 | }; | |
165 | }; | |
166 | ||
167 | port@2 { | |
168 | reg = <1>; | |
169 | funnel_in_port1: endpoint { | |
170 | slave-mode; | |
171 | remote-endpoint = <&ptm1_out_port>; | |
172 | }; | |
173 | }; | |
174 | ||
175 | port@3 { | |
176 | reg = <2>; | |
177 | funnel_in_port2: endpoint { | |
178 | slave-mode; | |
179 | remote-endpoint = <&etm0_out_port>; | |
180 | }; | |
181 | }; | |
182 | ||
183 | }; | |
184 | }; | |
185 | ||
186 | 3. Sources | |
187 | ptm@2201c000 { | |
188 | compatible = "arm,coresight-etm3x", "arm,primecell"; | |
189 | reg = <0 0x2201c000 0 0x1000>; | |
190 | ||
191 | cpu = <&cpu0>; | |
192 | clocks = <&oscclk6a>; | |
193 | clock-names = "apb_pclk"; | |
194 | port { | |
195 | ptm0_out_port: endpoint { | |
196 | remote-endpoint = <&funnel_in_port0>; | |
197 | }; | |
198 | }; | |
199 | }; | |
200 | ||
201 | ptm@2201d000 { | |
202 | compatible = "arm,coresight-etm3x", "arm,primecell"; | |
203 | reg = <0 0x2201d000 0 0x1000>; | |
204 | ||
205 | cpu = <&cpu1>; | |
206 | clocks = <&oscclk6a>; | |
207 | clock-names = "apb_pclk"; | |
208 | port { | |
209 | ptm1_out_port: endpoint { | |
210 | remote-endpoint = <&funnel_in_port1>; | |
211 | }; | |
212 | }; | |
213 | }; | |
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214 | |
215 | 4. STM | |
216 | stm@20100000 { | |
217 | compatible = "arm,coresight-stm", "arm,primecell"; | |
218 | reg = <0 0x20100000 0 0x1000>, | |
219 | <0 0x28000000 0 0x180000>; | |
220 | reg-names = "stm-base", "stm-stimulus-base"; | |
221 | ||
222 | clocks = <&soc_smc50mhz>; | |
223 | clock-names = "apb_pclk"; | |
224 | port { | |
225 | stm_out_port: endpoint { | |
226 | remote-endpoint = <&main_funnel_in_port2>; | |
227 | }; | |
228 | }; | |
229 | }; | |
230 | ||
231 | [1]. There is currently two version of STM: STM32 and STM500. Both | |
232 | have the same HW interface and as such don't need an explicit binding name. |