projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 799656de MP |
1 | * CoreSight Components: |
| 2 | ||
| 3 | CoreSight components are compliant with the ARM CoreSight architecture | |
| 4 | specification and can be connected in various topologies to suit a particular | |
| 5 | SoCs tracing needs. These trace components can generally be classified as | |
| 6 | sinks, links and sources. Trace data produced by one or more sources flows | |
| 7 | through the intermediate links connecting the source to the currently selected | |
| 8 | sink. Each CoreSight component device should use these properties to describe | |
| 9 | its hardware characteristcs. | |
| 10 | ||
| 11 | * Required properties for all components *except* non-configurable replicators: | |
| 12 | ||
| 13 | * compatible: These have to be supplemented with "arm,primecell" as | |
| 14 | drivers are using the AMBA bus interface. Possible values include: | |
| 4b681efc | 15 | - Embedded Trace Buffer (version 1.0): |
| 16 | "arm,coresight-etb10", "arm,primecell"; | |
| 17 | ||
| 18 | - Trace Port Interface Unit: | |
| 19 | "arm,coresight-tpiu", "arm,primecell"; | |
| 20 | ||
| 21 | - Trace Memory Controller, used for Embedded Trace Buffer(ETB), | |
| 22 | Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) | |
| 23 | configuration. The configuration mode (ETB, ETF, ETR) is | |
| 24 | discovered at boot time when the device is probed. | |
| 25 | "arm,coresight-tmc", "arm,primecell"; | |
| 26 | ||
| 27 | - Trace Funnel: | |
| 28 | "arm,coresight-funnel", "arm,primecell"; | |
| 29 | ||
| 30 | - Embedded Trace Macrocell (version 3.x) and | |
| 31 | Program Flow Trace Macrocell: | |
| 32 | "arm,coresight-etm3x", "arm,primecell"; | |
| 33 | ||
| 34 | - Embedded Trace Macrocell (version 4.x): | |
| 35 | "arm,coresight-etm4x", "arm,primecell"; | |
| 36 | ||
| 37 | - Qualcomm Configurable Replicator (version 1.x): | |
| 38 | "qcom,coresight-replicator1x", "arm,primecell"; | |
| 39 | ||
| 40 | - System Trace Macrocell: | |
| 41 | "arm,coresight-stm", "arm,primecell"; [1] | |
| 799656de MP |
42 | |
| 43 | * reg: physical base address and length of the register | |
| 44 | set(s) of the component. | |
| 45 | ||
| 70dd9d2f LW |
46 | * clocks: the clocks associated to this component. |
| 47 | ||
| 48 | * clock-names: the name of the clocks referenced by the code. | |
| 49 | Since we are using the AMBA framework, the name of the clock | |
| 50 | providing the interconnect should be "apb_pclk", and some | |
| 51 | coresight blocks also have an additional clock "atclk", which | |
| 52 | clocks the core of that coresight component. The latter clock | |
| 53 | is optional. | |
| 799656de MP |
54 | |
| 55 | * port or ports: The representation of the component's port | |
| 56 | layout using the generic DT graph presentation found in | |
| 57 | "bindings/graph.txt". | |
| 58 | ||
| 9eb93313 MP |
59 | * Additional required properties for System Trace Macrocells (STM): |
| 60 | * reg: along with the physical base address and length of the register | |
| 61 | set as described above, another entry is required to describe the | |
| 62 | mapping of the extended stimulus port area. | |
| 63 | ||
| 64 | * reg-names: the only acceptable values are "stm-base" and | |
| 65 | "stm-stimulus-base", each corresponding to the areas defined in "reg". | |
| 66 | ||
| 799656de MP |
67 | * Required properties for devices that don't show up on the AMBA bus, such as |
| 68 | non-configurable replicators: | |
| 69 | ||
| 70 | * compatible: Currently supported value is (note the absence of the | |
| 71 | AMBA markee): | |
| 72 | - "arm,coresight-replicator" | |
| 73 | ||
| 799656de MP |
74 | * port or ports: same as above. |
| 75 | ||
| 76 | * Optional properties for ETM/PTMs: | |
| 77 | ||
| 78 | * arm,cp14: must be present if the system accesses ETM/PTM management | |
| 79 | registers via co-processor 14. | |
| 80 | ||
| 81 | * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the | |
| 82 | source is considered to belong to CPU0. | |
| 83 | ||
| 84 | * Optional property for TMC: | |
| 85 | ||
| 86 | * arm,buffer-size: size of contiguous buffer space for TMC ETR | |
| 87 | (embedded trace router) | |
| 88 | ||
| 89 | ||
| 90 | Example: | |
| 91 | ||
| 92 | 1. Sinks | |
| 93 | etb@20010000 { | |
| 94 | compatible = "arm,coresight-etb10", "arm,primecell"; | |
| 95 | reg = <0 0x20010000 0 0x1000>; | |
| 96 | ||
| 799656de MP |
97 | clocks = <&oscclk6a>; |
| 98 | clock-names = "apb_pclk"; | |
| 99 | port { | |
| 100 | etb_in_port: endpoint@0 { | |
| 101 | slave-mode; | |
| 102 | remote-endpoint = <&replicator_out_port0>; | |
| 103 | }; | |
| 104 | }; | |
| 105 | }; | |
| 106 | ||
| 107 | tpiu@20030000 { | |
| 108 | compatible = "arm,coresight-tpiu", "arm,primecell"; | |
| 109 | reg = <0 0x20030000 0 0x1000>; | |
| 110 | ||
| 111 | clocks = <&oscclk6a>; | |
| 112 | clock-names = "apb_pclk"; | |
| 113 | port { | |
| 114 | tpiu_in_port: endpoint@0 { | |
| 115 | slave-mode; | |
| 116 | remote-endpoint = <&replicator_out_port1>; | |
| 117 | }; | |
| 118 | }; | |
| 119 | }; | |
| 120 | ||
| 121 | 2. Links | |
| 122 | replicator { | |
| 123 | /* non-configurable replicators don't show up on the | |
| 124 | * AMBA bus. As such no need to add "arm,primecell". | |
| 125 | */ | |
| 126 | compatible = "arm,coresight-replicator"; | |
| 799656de MP |
127 | |
| 128 | ports { | |
| 129 | #address-cells = <1>; | |
| 130 | #size-cells = <0>; | |
| 131 | ||
| 132 | /* replicator output ports */ | |
| 133 | port@0 { | |
| 134 | reg = <0>; | |
| 135 | replicator_out_port0: endpoint { | |
| 136 | remote-endpoint = <&etb_in_port>; | |
| 137 | }; | |
| 138 | }; | |
| 139 | ||
| 140 | port@1 { | |
| 141 | reg = <1>; | |
| 142 | replicator_out_port1: endpoint { | |
| 143 | remote-endpoint = <&tpiu_in_port>; | |
| 144 | }; | |
| 145 | }; | |
| 146 | ||
| 147 | /* replicator input port */ | |
| 148 | port@2 { | |
| 149 | reg = <0>; | |
| 150 | replicator_in_port0: endpoint { | |
| 151 | slave-mode; | |
| 152 | remote-endpoint = <&funnel_out_port0>; | |
| 153 | }; | |
| 154 | }; | |
| 155 | }; | |
| 156 | }; | |
| 157 | ||
| 158 | funnel@20040000 { | |
| 159 | compatible = "arm,coresight-funnel", "arm,primecell"; | |
| 160 | reg = <0 0x20040000 0 0x1000>; | |
| 161 | ||
| 162 | clocks = <&oscclk6a>; | |
| 163 | clock-names = "apb_pclk"; | |
| 164 | ports { | |
| 165 | #address-cells = <1>; | |
| 166 | #size-cells = <0>; | |
| 167 | ||
| 168 | /* funnel output port */ | |
| 169 | port@0 { | |
| 170 | reg = <0>; | |
| 171 | funnel_out_port0: endpoint { | |
| 172 | remote-endpoint = | |
| 173 | <&replicator_in_port0>; | |
| 174 | }; | |
| 175 | }; | |
| 176 | ||
| 177 | /* funnel input ports */ | |
| 178 | port@1 { | |
| 179 | reg = <0>; | |
| 180 | funnel_in_port0: endpoint { | |
| 181 | slave-mode; | |
| 182 | remote-endpoint = <&ptm0_out_port>; | |
| 183 | }; | |
| 184 | }; | |
| 185 | ||
| 186 | port@2 { | |
| 187 | reg = <1>; | |
| 188 | funnel_in_port1: endpoint { | |
| 189 | slave-mode; | |
| 190 | remote-endpoint = <&ptm1_out_port>; | |
| 191 | }; | |
| 192 | }; | |
| 193 | ||
| 194 | port@3 { | |
| 195 | reg = <2>; | |
| 196 | funnel_in_port2: endpoint { | |
| 197 | slave-mode; | |
| 198 | remote-endpoint = <&etm0_out_port>; | |
| 199 | }; | |
| 200 | }; | |
| 201 | ||
| 202 | }; | |
| 203 | }; | |
| 204 | ||
| 205 | 3. Sources | |
| 206 | ptm@2201c000 { | |
| 207 | compatible = "arm,coresight-etm3x", "arm,primecell"; | |
| 208 | reg = <0 0x2201c000 0 0x1000>; | |
| 209 | ||
| 210 | cpu = <&cpu0>; | |
| 211 | clocks = <&oscclk6a>; | |
| 212 | clock-names = "apb_pclk"; | |
| 213 | port { | |
| 214 | ptm0_out_port: endpoint { | |
| 215 | remote-endpoint = <&funnel_in_port0>; | |
| 216 | }; | |
| 217 | }; | |
| 218 | }; | |
| 219 | ||
| 220 | ptm@2201d000 { | |
| 221 | compatible = "arm,coresight-etm3x", "arm,primecell"; | |
| 222 | reg = <0 0x2201d000 0 0x1000>; | |
| 223 | ||
| 224 | cpu = <&cpu1>; | |
| 225 | clocks = <&oscclk6a>; | |
| 226 | clock-names = "apb_pclk"; | |
| 227 | port { | |
| 228 | ptm1_out_port: endpoint { | |
| 229 | remote-endpoint = <&funnel_in_port1>; | |
| 230 | }; | |
| 231 | }; | |
| 232 | }; | |
| 9eb93313 MP |
233 | |
| 234 | 4. STM | |
| 235 | stm@20100000 { | |
| 236 | compatible = "arm,coresight-stm", "arm,primecell"; | |
| 237 | reg = <0 0x20100000 0 0x1000>, | |
| 238 | <0 0x28000000 0 0x180000>; | |
| 239 | reg-names = "stm-base", "stm-stimulus-base"; | |
| 240 | ||
| 241 | clocks = <&soc_smc50mhz>; | |
| 242 | clock-names = "apb_pclk"; | |
| 243 | port { | |
| 244 | stm_out_port: endpoint { | |
| 245 | remote-endpoint = <&main_funnel_in_port2>; | |
| 246 | }; | |
| 247 | }; | |
| 248 | }; | |
| 249 | ||
| 250 | [1]. There is currently two version of STM: STM32 and STM500. Both | |
| 251 | have the same HW interface and as such don't need an explicit binding name. |