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594f88d1 LP |
1 | ================= |
2 | ARM CPUs bindings | |
3 | ================= | |
a0ae0240 LP |
4 | |
5 | The device tree allows to describe the layout of CPUs in a system through | |
6 | the "cpus" node, which in turn contains a number of subnodes (ie "cpu") | |
7 | defining properties for every cpu. | |
8 | ||
594f88d1 LP |
9 | Bindings for CPU nodes follow the ePAPR v1.1 standard, available from: |
10 | ||
11 | https://www.power.org/documentation/epapr-version-1-1/ | |
12 | ||
13 | with updates for 32-bit and 64-bit ARM systems provided in this document. | |
14 | ||
15 | ================================ | |
16 | Convention used in this document | |
17 | ================================ | |
18 | ||
19 | This document follows the conventions described in the ePAPR v1.1, with | |
20 | the addition: | |
21 | ||
22 | - square brackets define bitfields, eg reg[7:0] value of the bitfield in | |
23 | the reg property contained in bits 7 down to 0 | |
24 | ||
25 | ===================================== | |
26 | cpus and cpu node bindings definition | |
27 | ===================================== | |
28 | ||
29 | The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu | |
30 | nodes to be present and contain the properties described below. | |
31 | ||
32 | - cpus node | |
33 | ||
34 | Description: Container of cpu nodes | |
35 | ||
36 | The node name must be "cpus". | |
37 | ||
38 | A cpus node must define the following properties: | |
39 | ||
40 | - #address-cells | |
41 | Usage: required | |
42 | Value type: <u32> | |
43 | ||
44 | Definition depends on ARM architecture version and | |
45 | configuration: | |
46 | ||
47 | # On uniprocessor ARM architectures previous to v7 | |
48 | value must be 1, to enable a simple enumeration | |
49 | scheme for processors that do not have a HW CPU | |
50 | identification register. | |
51 | # On 32-bit ARM 11 MPcore, ARM v7 or later systems | |
52 | value must be 1, that corresponds to CPUID/MPIDR | |
53 | registers sizes. | |
54 | # On ARM v8 64-bit systems value should be set to 2, | |
55 | that corresponds to the MPIDR_EL1 register size. | |
56 | If MPIDR_EL1[63:32] value is equal to 0 on all CPUs | |
57 | in the system, #address-cells can be set to 1, since | |
58 | MPIDR_EL1[63:32] bits are not used for CPUs | |
59 | identification. | |
60 | - #size-cells | |
61 | Usage: required | |
62 | Value type: <u32> | |
63 | Definition: must be set to 0 | |
64 | ||
65 | - cpu node | |
66 | ||
67 | Description: Describes a CPU in an ARM based system | |
68 | ||
69 | PROPERTIES | |
70 | ||
71 | - device_type | |
72 | Usage: required | |
73 | Value type: <string> | |
74 | Definition: must be "cpu" | |
75 | - reg | |
76 | Usage and definition depend on ARM architecture version and | |
77 | configuration: | |
78 | ||
79 | # On uniprocessor ARM architectures previous to v7 | |
80 | this property is required and must be set to 0. | |
81 | ||
82 | # On ARM 11 MPcore based systems this property is | |
83 | required and matches the CPUID[11:0] register bits. | |
84 | ||
85 | Bits [11:0] in the reg cell must be set to | |
86 | bits [11:0] in CPU ID register. | |
87 | ||
88 | All other bits in the reg cell must be set to 0. | |
89 | ||
90 | # On 32-bit ARM v7 or later systems this property is | |
91 | required and matches the CPU MPIDR[23:0] register | |
92 | bits. | |
93 | ||
94 | Bits [23:0] in the reg cell must be set to | |
95 | bits [23:0] in MPIDR. | |
96 | ||
97 | All other bits in the reg cell must be set to 0. | |
98 | ||
99 | # On ARM v8 64-bit systems this property is required | |
100 | and matches the MPIDR_EL1 register affinity bits. | |
101 | ||
102 | * If cpus node's #address-cells property is set to 2 | |
103 | ||
104 | The first reg cell bits [7:0] must be set to | |
105 | bits [39:32] of MPIDR_EL1. | |
106 | ||
107 | The second reg cell bits [23:0] must be set to | |
108 | bits [23:0] of MPIDR_EL1. | |
109 | ||
110 | * If cpus node's #address-cells property is set to 1 | |
111 | ||
112 | The reg cell bits [23:0] must be set to bits [23:0] | |
113 | of MPIDR_EL1. | |
114 | ||
115 | All other bits in the reg cells must be set to 0. | |
116 | ||
117 | - compatible: | |
118 | Usage: required | |
119 | Value type: <string> | |
120 | Definition: should be one of: | |
121 | "arm,arm710t" | |
122 | "arm,arm720t" | |
123 | "arm,arm740t" | |
124 | "arm,arm7ej-s" | |
125 | "arm,arm7tdmi" | |
126 | "arm,arm7tdmi-s" | |
127 | "arm,arm9es" | |
128 | "arm,arm9ej-s" | |
129 | "arm,arm920t" | |
130 | "arm,arm922t" | |
131 | "arm,arm925" | |
132 | "arm,arm926e-s" | |
133 | "arm,arm926ej-s" | |
134 | "arm,arm940t" | |
135 | "arm,arm946e-s" | |
136 | "arm,arm966e-s" | |
137 | "arm,arm968e-s" | |
138 | "arm,arm9tdmi" | |
139 | "arm,arm1020e" | |
140 | "arm,arm1020t" | |
141 | "arm,arm1022e" | |
142 | "arm,arm1026ej-s" | |
143 | "arm,arm1136j-s" | |
144 | "arm,arm1136jf-s" | |
145 | "arm,arm1156t2-s" | |
146 | "arm,arm1156t2f-s" | |
147 | "arm,arm1176jzf" | |
148 | "arm,arm1176jz-s" | |
149 | "arm,arm1176jzf-s" | |
150 | "arm,arm11mpcore" | |
151 | "arm,cortex-a5" | |
152 | "arm,cortex-a7" | |
153 | "arm,cortex-a8" | |
154 | "arm,cortex-a9" | |
198946b1 | 155 | "arm,cortex-a12" |
594f88d1 | 156 | "arm,cortex-a15" |
198946b1 | 157 | "arm,cortex-a17" |
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158 | "arm,cortex-a53" |
159 | "arm,cortex-a57" | |
160 | "arm,cortex-m0" | |
161 | "arm,cortex-m0+" | |
162 | "arm,cortex-m1" | |
163 | "arm,cortex-m3" | |
164 | "arm,cortex-m4" | |
165 | "arm,cortex-r4" | |
166 | "arm,cortex-r5" | |
167 | "arm,cortex-r7" | |
0a540d4b | 168 | "brcm,brahma-b15" |
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169 | "faraday,fa526" |
170 | "intel,sa110" | |
171 | "intel,sa1100" | |
172 | "marvell,feroceon" | |
173 | "marvell,mohawk" | |
174 | "marvell,pj4a" | |
175 | "marvell,pj4b" | |
176 | "marvell,sheeva-v5" | |
177 | "qcom,krait" | |
178 | "qcom,scorpion" | |
179 | - enable-method | |
180 | Value type: <stringlist> | |
181 | Usage and definition depend on ARM architecture version. | |
182 | # On ARM v8 64-bit this property is required and must | |
183 | be one of: | |
594f88d1 | 184 | "psci" |
e1dc566f | 185 | "spin-table" |
b00c927d RV |
186 | # On ARM 32-bit systems this property is optional and |
187 | can be one of: | |
913627b3 | 188 | "allwinner,sun6i-a31" |
e1dc566f | 189 | "arm,psci" |
0a540d4b | 190 | "brcm,brahma-b15" |
1ee89e22 GC |
191 | "marvell,armada-375-smp" |
192 | "marvell,armada-380-smp" | |
2c9b2240 | 193 | "marvell,armada-xp-smp" |
e1dc566f OJ |
194 | "qcom,gcc-msm8660" |
195 | "qcom,kpss-acc-v1" | |
196 | "qcom,kpss-acc-v2" | |
26ab69cb | 197 | "rockchip,rk3066-smp" |
594f88d1 LP |
198 | |
199 | - cpu-release-addr | |
200 | Usage: required for systems that have an "enable-method" | |
201 | property value of "spin-table". | |
202 | Value type: <prop-encoded-array> | |
203 | Definition: | |
204 | # On ARM v8 64-bit systems must be a two cell | |
205 | property identifying a 64-bit zero-initialised | |
206 | memory location. | |
207 | ||
b00c927d RV |
208 | - qcom,saw |
209 | Usage: required for systems that have an "enable-method" | |
210 | property value of "qcom,kpss-acc-v1" or | |
211 | "qcom,kpss-acc-v2" | |
212 | Value type: <phandle> | |
213 | Definition: Specifies the SAW[1] node associated with this CPU. | |
214 | ||
215 | - qcom,acc | |
216 | Usage: required for systems that have an "enable-method" | |
217 | property value of "qcom,kpss-acc-v1" or | |
218 | "qcom,kpss-acc-v2" | |
219 | Value type: <phandle> | |
220 | Definition: Specifies the ACC[2] node associated with this CPU. | |
221 | ||
222 | ||
594f88d1 | 223 | Example 1 (dual-cluster big.LITTLE system 32-bit): |
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224 | |
225 | cpus { | |
226 | #size-cells = <0>; | |
227 | #address-cells = <1>; | |
228 | ||
594f88d1 | 229 | cpu@0 { |
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230 | device_type = "cpu"; |
231 | compatible = "arm,cortex-a15"; | |
232 | reg = <0x0>; | |
233 | }; | |
234 | ||
594f88d1 | 235 | cpu@1 { |
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236 | device_type = "cpu"; |
237 | compatible = "arm,cortex-a15"; | |
238 | reg = <0x1>; | |
239 | }; | |
240 | ||
594f88d1 | 241 | cpu@100 { |
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242 | device_type = "cpu"; |
243 | compatible = "arm,cortex-a7"; | |
244 | reg = <0x100>; | |
245 | }; | |
246 | ||
594f88d1 | 247 | cpu@101 { |
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248 | device_type = "cpu"; |
249 | compatible = "arm,cortex-a7"; | |
250 | reg = <0x101>; | |
251 | }; | |
252 | }; | |
594f88d1 LP |
253 | |
254 | Example 2 (Cortex-A8 uniprocessor 32-bit system): | |
255 | ||
256 | cpus { | |
257 | #size-cells = <0>; | |
258 | #address-cells = <1>; | |
259 | ||
260 | cpu@0 { | |
261 | device_type = "cpu"; | |
262 | compatible = "arm,cortex-a8"; | |
263 | reg = <0x0>; | |
264 | }; | |
265 | }; | |
266 | ||
267 | Example 3 (ARM 926EJ-S uniprocessor 32-bit system): | |
268 | ||
269 | cpus { | |
270 | #size-cells = <0>; | |
271 | #address-cells = <1>; | |
272 | ||
273 | cpu@0 { | |
274 | device_type = "cpu"; | |
275 | compatible = "arm,arm926ej-s"; | |
276 | reg = <0x0>; | |
277 | }; | |
278 | }; | |
279 | ||
280 | Example 4 (ARM Cortex-A57 64-bit system): | |
281 | ||
282 | cpus { | |
283 | #size-cells = <0>; | |
284 | #address-cells = <2>; | |
285 | ||
286 | cpu@0 { | |
287 | device_type = "cpu"; | |
288 | compatible = "arm,cortex-a57"; | |
289 | reg = <0x0 0x0>; | |
290 | enable-method = "spin-table"; | |
291 | cpu-release-addr = <0 0x20000000>; | |
292 | }; | |
293 | ||
294 | cpu@1 { | |
295 | device_type = "cpu"; | |
296 | compatible = "arm,cortex-a57"; | |
297 | reg = <0x0 0x1>; | |
298 | enable-method = "spin-table"; | |
299 | cpu-release-addr = <0 0x20000000>; | |
300 | }; | |
301 | ||
302 | cpu@100 { | |
303 | device_type = "cpu"; | |
304 | compatible = "arm,cortex-a57"; | |
305 | reg = <0x0 0x100>; | |
306 | enable-method = "spin-table"; | |
307 | cpu-release-addr = <0 0x20000000>; | |
308 | }; | |
309 | ||
310 | cpu@101 { | |
311 | device_type = "cpu"; | |
312 | compatible = "arm,cortex-a57"; | |
313 | reg = <0x0 0x101>; | |
314 | enable-method = "spin-table"; | |
315 | cpu-release-addr = <0 0x20000000>; | |
316 | }; | |
317 | ||
318 | cpu@10000 { | |
319 | device_type = "cpu"; | |
320 | compatible = "arm,cortex-a57"; | |
321 | reg = <0x0 0x10000>; | |
322 | enable-method = "spin-table"; | |
323 | cpu-release-addr = <0 0x20000000>; | |
324 | }; | |
325 | ||
326 | cpu@10001 { | |
327 | device_type = "cpu"; | |
328 | compatible = "arm,cortex-a57"; | |
329 | reg = <0x0 0x10001>; | |
330 | enable-method = "spin-table"; | |
331 | cpu-release-addr = <0 0x20000000>; | |
332 | }; | |
333 | ||
334 | cpu@10100 { | |
335 | device_type = "cpu"; | |
336 | compatible = "arm,cortex-a57"; | |
337 | reg = <0x0 0x10100>; | |
338 | enable-method = "spin-table"; | |
339 | cpu-release-addr = <0 0x20000000>; | |
340 | }; | |
341 | ||
342 | cpu@10101 { | |
343 | device_type = "cpu"; | |
344 | compatible = "arm,cortex-a57"; | |
345 | reg = <0x0 0x10101>; | |
346 | enable-method = "spin-table"; | |
347 | cpu-release-addr = <0 0x20000000>; | |
348 | }; | |
349 | ||
350 | cpu@100000000 { | |
351 | device_type = "cpu"; | |
352 | compatible = "arm,cortex-a57"; | |
353 | reg = <0x1 0x0>; | |
354 | enable-method = "spin-table"; | |
355 | cpu-release-addr = <0 0x20000000>; | |
356 | }; | |
357 | ||
358 | cpu@100000001 { | |
359 | device_type = "cpu"; | |
360 | compatible = "arm,cortex-a57"; | |
361 | reg = <0x1 0x1>; | |
362 | enable-method = "spin-table"; | |
363 | cpu-release-addr = <0 0x20000000>; | |
364 | }; | |
365 | ||
366 | cpu@100000100 { | |
367 | device_type = "cpu"; | |
368 | compatible = "arm,cortex-a57"; | |
369 | reg = <0x1 0x100>; | |
370 | enable-method = "spin-table"; | |
371 | cpu-release-addr = <0 0x20000000>; | |
372 | }; | |
373 | ||
374 | cpu@100000101 { | |
375 | device_type = "cpu"; | |
376 | compatible = "arm,cortex-a57"; | |
377 | reg = <0x1 0x101>; | |
378 | enable-method = "spin-table"; | |
379 | cpu-release-addr = <0 0x20000000>; | |
380 | }; | |
381 | ||
382 | cpu@100010000 { | |
383 | device_type = "cpu"; | |
384 | compatible = "arm,cortex-a57"; | |
385 | reg = <0x1 0x10000>; | |
386 | enable-method = "spin-table"; | |
387 | cpu-release-addr = <0 0x20000000>; | |
388 | }; | |
389 | ||
390 | cpu@100010001 { | |
391 | device_type = "cpu"; | |
392 | compatible = "arm,cortex-a57"; | |
393 | reg = <0x1 0x10001>; | |
394 | enable-method = "spin-table"; | |
395 | cpu-release-addr = <0 0x20000000>; | |
396 | }; | |
397 | ||
398 | cpu@100010100 { | |
399 | device_type = "cpu"; | |
400 | compatible = "arm,cortex-a57"; | |
401 | reg = <0x1 0x10100>; | |
402 | enable-method = "spin-table"; | |
403 | cpu-release-addr = <0 0x20000000>; | |
404 | }; | |
405 | ||
406 | cpu@100010101 { | |
407 | device_type = "cpu"; | |
408 | compatible = "arm,cortex-a57"; | |
409 | reg = <0x1 0x10101>; | |
410 | enable-method = "spin-table"; | |
411 | cpu-release-addr = <0 0x20000000>; | |
412 | }; | |
413 | }; | |
b00c927d RV |
414 | |
415 | -- | |
416 | [1] arm/msm/qcom,saw2.txt | |
417 | [2] arm/msm/qcom,kpss-acc.txt |