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594f88d1 LP |
1 | ================= |
2 | ARM CPUs bindings | |
3 | ================= | |
a0ae0240 LP |
4 | |
5 | The device tree allows to describe the layout of CPUs in a system through | |
6 | the "cpus" node, which in turn contains a number of subnodes (ie "cpu") | |
7 | defining properties for every cpu. | |
8 | ||
594f88d1 LP |
9 | Bindings for CPU nodes follow the ePAPR v1.1 standard, available from: |
10 | ||
11 | https://www.power.org/documentation/epapr-version-1-1/ | |
12 | ||
13 | with updates for 32-bit and 64-bit ARM systems provided in this document. | |
14 | ||
15 | ================================ | |
16 | Convention used in this document | |
17 | ================================ | |
18 | ||
19 | This document follows the conventions described in the ePAPR v1.1, with | |
20 | the addition: | |
21 | ||
22 | - square brackets define bitfields, eg reg[7:0] value of the bitfield in | |
23 | the reg property contained in bits 7 down to 0 | |
24 | ||
25 | ===================================== | |
26 | cpus and cpu node bindings definition | |
27 | ===================================== | |
28 | ||
29 | The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu | |
30 | nodes to be present and contain the properties described below. | |
31 | ||
32 | - cpus node | |
33 | ||
34 | Description: Container of cpu nodes | |
35 | ||
36 | The node name must be "cpus". | |
37 | ||
38 | A cpus node must define the following properties: | |
39 | ||
40 | - #address-cells | |
41 | Usage: required | |
42 | Value type: <u32> | |
43 | ||
44 | Definition depends on ARM architecture version and | |
45 | configuration: | |
46 | ||
47 | # On uniprocessor ARM architectures previous to v7 | |
48 | value must be 1, to enable a simple enumeration | |
49 | scheme for processors that do not have a HW CPU | |
50 | identification register. | |
51 | # On 32-bit ARM 11 MPcore, ARM v7 or later systems | |
52 | value must be 1, that corresponds to CPUID/MPIDR | |
53 | registers sizes. | |
54 | # On ARM v8 64-bit systems value should be set to 2, | |
55 | that corresponds to the MPIDR_EL1 register size. | |
56 | If MPIDR_EL1[63:32] value is equal to 0 on all CPUs | |
57 | in the system, #address-cells can be set to 1, since | |
58 | MPIDR_EL1[63:32] bits are not used for CPUs | |
59 | identification. | |
60 | - #size-cells | |
61 | Usage: required | |
62 | Value type: <u32> | |
63 | Definition: must be set to 0 | |
64 | ||
65 | - cpu node | |
66 | ||
67 | Description: Describes a CPU in an ARM based system | |
68 | ||
69 | PROPERTIES | |
70 | ||
71 | - device_type | |
72 | Usage: required | |
73 | Value type: <string> | |
74 | Definition: must be "cpu" | |
75 | - reg | |
76 | Usage and definition depend on ARM architecture version and | |
77 | configuration: | |
78 | ||
79 | # On uniprocessor ARM architectures previous to v7 | |
80 | this property is required and must be set to 0. | |
81 | ||
82 | # On ARM 11 MPcore based systems this property is | |
83 | required and matches the CPUID[11:0] register bits. | |
84 | ||
85 | Bits [11:0] in the reg cell must be set to | |
86 | bits [11:0] in CPU ID register. | |
87 | ||
88 | All other bits in the reg cell must be set to 0. | |
89 | ||
90 | # On 32-bit ARM v7 or later systems this property is | |
91 | required and matches the CPU MPIDR[23:0] register | |
92 | bits. | |
93 | ||
94 | Bits [23:0] in the reg cell must be set to | |
95 | bits [23:0] in MPIDR. | |
96 | ||
97 | All other bits in the reg cell must be set to 0. | |
98 | ||
99 | # On ARM v8 64-bit systems this property is required | |
100 | and matches the MPIDR_EL1 register affinity bits. | |
101 | ||
102 | * If cpus node's #address-cells property is set to 2 | |
103 | ||
104 | The first reg cell bits [7:0] must be set to | |
105 | bits [39:32] of MPIDR_EL1. | |
106 | ||
107 | The second reg cell bits [23:0] must be set to | |
108 | bits [23:0] of MPIDR_EL1. | |
109 | ||
110 | * If cpus node's #address-cells property is set to 1 | |
111 | ||
112 | The reg cell bits [23:0] must be set to bits [23:0] | |
113 | of MPIDR_EL1. | |
114 | ||
115 | All other bits in the reg cells must be set to 0. | |
116 | ||
117 | - compatible: | |
118 | Usage: required | |
119 | Value type: <string> | |
120 | Definition: should be one of: | |
121 | "arm,arm710t" | |
122 | "arm,arm720t" | |
123 | "arm,arm740t" | |
124 | "arm,arm7ej-s" | |
125 | "arm,arm7tdmi" | |
126 | "arm,arm7tdmi-s" | |
127 | "arm,arm9es" | |
128 | "arm,arm9ej-s" | |
129 | "arm,arm920t" | |
130 | "arm,arm922t" | |
131 | "arm,arm925" | |
132 | "arm,arm926e-s" | |
133 | "arm,arm926ej-s" | |
134 | "arm,arm940t" | |
135 | "arm,arm946e-s" | |
136 | "arm,arm966e-s" | |
137 | "arm,arm968e-s" | |
138 | "arm,arm9tdmi" | |
139 | "arm,arm1020e" | |
140 | "arm,arm1020t" | |
141 | "arm,arm1022e" | |
142 | "arm,arm1026ej-s" | |
143 | "arm,arm1136j-s" | |
144 | "arm,arm1136jf-s" | |
145 | "arm,arm1156t2-s" | |
146 | "arm,arm1156t2f-s" | |
147 | "arm,arm1176jzf" | |
148 | "arm,arm1176jz-s" | |
149 | "arm,arm1176jzf-s" | |
150 | "arm,arm11mpcore" | |
151 | "arm,cortex-a5" | |
152 | "arm,cortex-a7" | |
153 | "arm,cortex-a8" | |
154 | "arm,cortex-a9" | |
198946b1 | 155 | "arm,cortex-a12" |
594f88d1 | 156 | "arm,cortex-a15" |
198946b1 | 157 | "arm,cortex-a17" |
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158 | "arm,cortex-a53" |
159 | "arm,cortex-a57" | |
160 | "arm,cortex-m0" | |
161 | "arm,cortex-m0+" | |
162 | "arm,cortex-m1" | |
163 | "arm,cortex-m3" | |
164 | "arm,cortex-m4" | |
165 | "arm,cortex-r4" | |
166 | "arm,cortex-r5" | |
167 | "arm,cortex-r7" | |
0a540d4b | 168 | "brcm,brahma-b15" |
4c308700 | 169 | "cavium,thunder" |
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170 | "faraday,fa526" |
171 | "intel,sa110" | |
172 | "intel,sa1100" | |
173 | "marvell,feroceon" | |
174 | "marvell,mohawk" | |
175 | "marvell,pj4a" | |
176 | "marvell,pj4b" | |
177 | "marvell,sheeva-v5" | |
178 | "qcom,krait" | |
179 | "qcom,scorpion" | |
180 | - enable-method | |
181 | Value type: <stringlist> | |
182 | Usage and definition depend on ARM architecture version. | |
183 | # On ARM v8 64-bit this property is required and must | |
184 | be one of: | |
594f88d1 | 185 | "psci" |
e1dc566f | 186 | "spin-table" |
b00c927d RV |
187 | # On ARM 32-bit systems this property is optional and |
188 | can be one of: | |
913627b3 | 189 | "allwinner,sun6i-a31" |
e1dc566f | 190 | "arm,psci" |
0a540d4b | 191 | "brcm,brahma-b15" |
1ee89e22 GC |
192 | "marvell,armada-375-smp" |
193 | "marvell,armada-380-smp" | |
2c9b2240 | 194 | "marvell,armada-xp-smp" |
e1dc566f OJ |
195 | "qcom,gcc-msm8660" |
196 | "qcom,kpss-acc-v1" | |
197 | "qcom,kpss-acc-v2" | |
26ab69cb | 198 | "rockchip,rk3066-smp" |
594f88d1 LP |
199 | |
200 | - cpu-release-addr | |
201 | Usage: required for systems that have an "enable-method" | |
202 | property value of "spin-table". | |
203 | Value type: <prop-encoded-array> | |
204 | Definition: | |
205 | # On ARM v8 64-bit systems must be a two cell | |
206 | property identifying a 64-bit zero-initialised | |
207 | memory location. | |
208 | ||
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209 | - qcom,saw |
210 | Usage: required for systems that have an "enable-method" | |
211 | property value of "qcom,kpss-acc-v1" or | |
212 | "qcom,kpss-acc-v2" | |
213 | Value type: <phandle> | |
214 | Definition: Specifies the SAW[1] node associated with this CPU. | |
215 | ||
216 | - qcom,acc | |
217 | Usage: required for systems that have an "enable-method" | |
218 | property value of "qcom,kpss-acc-v1" or | |
219 | "qcom,kpss-acc-v2" | |
220 | Value type: <phandle> | |
221 | Definition: Specifies the ACC[2] node associated with this CPU. | |
222 | ||
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223 | - cpu-idle-states |
224 | Usage: Optional | |
225 | Value type: <prop-encoded-array> | |
226 | Definition: | |
227 | # List of phandles to idle state nodes supported | |
228 | by this cpu [3]. | |
b00c927d | 229 | |
594f88d1 | 230 | Example 1 (dual-cluster big.LITTLE system 32-bit): |
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231 | |
232 | cpus { | |
233 | #size-cells = <0>; | |
234 | #address-cells = <1>; | |
235 | ||
594f88d1 | 236 | cpu@0 { |
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237 | device_type = "cpu"; |
238 | compatible = "arm,cortex-a15"; | |
239 | reg = <0x0>; | |
240 | }; | |
241 | ||
594f88d1 | 242 | cpu@1 { |
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243 | device_type = "cpu"; |
244 | compatible = "arm,cortex-a15"; | |
245 | reg = <0x1>; | |
246 | }; | |
247 | ||
594f88d1 | 248 | cpu@100 { |
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249 | device_type = "cpu"; |
250 | compatible = "arm,cortex-a7"; | |
251 | reg = <0x100>; | |
252 | }; | |
253 | ||
594f88d1 | 254 | cpu@101 { |
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255 | device_type = "cpu"; |
256 | compatible = "arm,cortex-a7"; | |
257 | reg = <0x101>; | |
258 | }; | |
259 | }; | |
594f88d1 LP |
260 | |
261 | Example 2 (Cortex-A8 uniprocessor 32-bit system): | |
262 | ||
263 | cpus { | |
264 | #size-cells = <0>; | |
265 | #address-cells = <1>; | |
266 | ||
267 | cpu@0 { | |
268 | device_type = "cpu"; | |
269 | compatible = "arm,cortex-a8"; | |
270 | reg = <0x0>; | |
271 | }; | |
272 | }; | |
273 | ||
274 | Example 3 (ARM 926EJ-S uniprocessor 32-bit system): | |
275 | ||
276 | cpus { | |
277 | #size-cells = <0>; | |
278 | #address-cells = <1>; | |
279 | ||
280 | cpu@0 { | |
281 | device_type = "cpu"; | |
282 | compatible = "arm,arm926ej-s"; | |
283 | reg = <0x0>; | |
284 | }; | |
285 | }; | |
286 | ||
287 | Example 4 (ARM Cortex-A57 64-bit system): | |
288 | ||
289 | cpus { | |
290 | #size-cells = <0>; | |
291 | #address-cells = <2>; | |
292 | ||
293 | cpu@0 { | |
294 | device_type = "cpu"; | |
295 | compatible = "arm,cortex-a57"; | |
296 | reg = <0x0 0x0>; | |
297 | enable-method = "spin-table"; | |
298 | cpu-release-addr = <0 0x20000000>; | |
299 | }; | |
300 | ||
301 | cpu@1 { | |
302 | device_type = "cpu"; | |
303 | compatible = "arm,cortex-a57"; | |
304 | reg = <0x0 0x1>; | |
305 | enable-method = "spin-table"; | |
306 | cpu-release-addr = <0 0x20000000>; | |
307 | }; | |
308 | ||
309 | cpu@100 { | |
310 | device_type = "cpu"; | |
311 | compatible = "arm,cortex-a57"; | |
312 | reg = <0x0 0x100>; | |
313 | enable-method = "spin-table"; | |
314 | cpu-release-addr = <0 0x20000000>; | |
315 | }; | |
316 | ||
317 | cpu@101 { | |
318 | device_type = "cpu"; | |
319 | compatible = "arm,cortex-a57"; | |
320 | reg = <0x0 0x101>; | |
321 | enable-method = "spin-table"; | |
322 | cpu-release-addr = <0 0x20000000>; | |
323 | }; | |
324 | ||
325 | cpu@10000 { | |
326 | device_type = "cpu"; | |
327 | compatible = "arm,cortex-a57"; | |
328 | reg = <0x0 0x10000>; | |
329 | enable-method = "spin-table"; | |
330 | cpu-release-addr = <0 0x20000000>; | |
331 | }; | |
332 | ||
333 | cpu@10001 { | |
334 | device_type = "cpu"; | |
335 | compatible = "arm,cortex-a57"; | |
336 | reg = <0x0 0x10001>; | |
337 | enable-method = "spin-table"; | |
338 | cpu-release-addr = <0 0x20000000>; | |
339 | }; | |
340 | ||
341 | cpu@10100 { | |
342 | device_type = "cpu"; | |
343 | compatible = "arm,cortex-a57"; | |
344 | reg = <0x0 0x10100>; | |
345 | enable-method = "spin-table"; | |
346 | cpu-release-addr = <0 0x20000000>; | |
347 | }; | |
348 | ||
349 | cpu@10101 { | |
350 | device_type = "cpu"; | |
351 | compatible = "arm,cortex-a57"; | |
352 | reg = <0x0 0x10101>; | |
353 | enable-method = "spin-table"; | |
354 | cpu-release-addr = <0 0x20000000>; | |
355 | }; | |
356 | ||
357 | cpu@100000000 { | |
358 | device_type = "cpu"; | |
359 | compatible = "arm,cortex-a57"; | |
360 | reg = <0x1 0x0>; | |
361 | enable-method = "spin-table"; | |
362 | cpu-release-addr = <0 0x20000000>; | |
363 | }; | |
364 | ||
365 | cpu@100000001 { | |
366 | device_type = "cpu"; | |
367 | compatible = "arm,cortex-a57"; | |
368 | reg = <0x1 0x1>; | |
369 | enable-method = "spin-table"; | |
370 | cpu-release-addr = <0 0x20000000>; | |
371 | }; | |
372 | ||
373 | cpu@100000100 { | |
374 | device_type = "cpu"; | |
375 | compatible = "arm,cortex-a57"; | |
376 | reg = <0x1 0x100>; | |
377 | enable-method = "spin-table"; | |
378 | cpu-release-addr = <0 0x20000000>; | |
379 | }; | |
380 | ||
381 | cpu@100000101 { | |
382 | device_type = "cpu"; | |
383 | compatible = "arm,cortex-a57"; | |
384 | reg = <0x1 0x101>; | |
385 | enable-method = "spin-table"; | |
386 | cpu-release-addr = <0 0x20000000>; | |
387 | }; | |
388 | ||
389 | cpu@100010000 { | |
390 | device_type = "cpu"; | |
391 | compatible = "arm,cortex-a57"; | |
392 | reg = <0x1 0x10000>; | |
393 | enable-method = "spin-table"; | |
394 | cpu-release-addr = <0 0x20000000>; | |
395 | }; | |
396 | ||
397 | cpu@100010001 { | |
398 | device_type = "cpu"; | |
399 | compatible = "arm,cortex-a57"; | |
400 | reg = <0x1 0x10001>; | |
401 | enable-method = "spin-table"; | |
402 | cpu-release-addr = <0 0x20000000>; | |
403 | }; | |
404 | ||
405 | cpu@100010100 { | |
406 | device_type = "cpu"; | |
407 | compatible = "arm,cortex-a57"; | |
408 | reg = <0x1 0x10100>; | |
409 | enable-method = "spin-table"; | |
410 | cpu-release-addr = <0 0x20000000>; | |
411 | }; | |
412 | ||
413 | cpu@100010101 { | |
414 | device_type = "cpu"; | |
415 | compatible = "arm,cortex-a57"; | |
416 | reg = <0x1 0x10101>; | |
417 | enable-method = "spin-table"; | |
418 | cpu-release-addr = <0 0x20000000>; | |
419 | }; | |
420 | }; | |
b00c927d RV |
421 | |
422 | -- | |
423 | [1] arm/msm/qcom,saw2.txt | |
424 | [2] arm/msm/qcom,kpss-acc.txt | |
3f8161b2 LP |
425 | [3] ARM Linux kernel documentation - idle states bindings |
426 | Documentation/devicetree/bindings/arm/idle-states.txt |