[deliverable/linux.git] / Documentation / devicetree / bindings / arm / exynos / power_domain.txt

* Samsung Exynos Power Domains

Exynos processors include support for multiple power domains which are used
to gate power to one or more peripherals on the processor.

Required Properties:
- compatible: should be one of the following.
    * samsung,exynos4210-pd - for exynos4210 type power domain.
- reg: physical base address of the controller and length of memory mapped
    region.
- #power-domain-cells: number of cells in power domain specifier;
    must be 0.

Optional Properties:
- clocks: List of clock handles. The parent clocks of the input clocks to the
	devices in this power domain are set to oscclk before power gating
	and restored back after powering on a domain. This is required for
	all domains which are powered on and off and not required for unused
	domains.
- clock-names: The following clocks can be specified:
	- oscclk: Oscillator clock.
	- pclkN, clkN: Pairs of parent of input clock and input clock to the
		devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
		are supported currently.
- power-domains: phandle pointing to the parent power domain, for more details
		 see Documentation/devicetree/bindings/power/power_domain.txt

Node of a device using power domains must have a power-domains property
defined with a phandle to respective power domain.

Example:

	lcd0: power-domain-lcd0 {
		compatible = "samsung,exynos4210-pd";
		reg = <0x10023C00 0x10>;
		#power-domain-cells = <0>;
	};

	mfc_pd: power-domain@10044060 {
		compatible = "samsung,exynos4210-pd";
		reg = <0x10044060 0x20>;
		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
			<&clock CLK_MOUT_USER_ACLK333>;
		clock-names = "oscclk", "pclk0", "clk0";
		#power-domain-cells = <0>;
	};

See Documentation/devicetree/bindings/power/power_domain.txt for description
of consumer-side bindings.
Commit	Line	Data
91cfbd4e TA	1	* Samsung Exynos Power Domains
	2
	3	Exynos processors include support for multiple power domains which are used
	4	to gate power to one or more peripherals on the processor.
	5
	6	Required Properties:
8a65d236	7	- compatible: should be one of the following.
91cfbd4e TA	8	* samsung,exynos4210-pd - for exynos4210 type power domain.
	9	- reg: physical base address of the controller and length of memory mapped
	10	region.
a4a8c2c4 TF	11	- #power-domain-cells: number of cells in power domain specifier;
a4a8c2c4 TF	12	must be 0.
91cfbd4e	13
c760569d P	14	Optional Properties:
	15	- clocks: List of clock handles. The parent clocks of the input clocks to the
	16	devices in this power domain are set to oscclk before power gating
	17	and restored back after powering on a domain. This is required for
	18	all domains which are powered on and off and not required for unused
	19	domains.
	20	- clock-names: The following clocks can be specified:
	21	- oscclk: Oscillator clock.
	22	- pclkN, clkN: Pairs of parent of input clock and input clock to the
	23	devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
	24	are supported currently.
0f780751 MS	25	- power-domains: phandle pointing to the parent power domain, for more details
0f780751 MS	26	see Documentation/devicetree/bindings/power/power_domain.txt
c760569d	27
0da65870	28	Node of a device using power domains must have a power-domains property
8a65d236 TF	29	defined with a phandle to respective power domain.
8a65d236 TF	30
91cfbd4e TA	31	Example:
	32
	33	lcd0: power-domain-lcd0 {
	34	compatible = "samsung,exynos4210-pd";
	35	reg = <0x10023C00 0x10>;
a4a8c2c4	36	#power-domain-cells = <0>;
91cfbd4e	37	};
8a65d236	38
c760569d P	39	mfc_pd: power-domain@10044060 {
	40	compatible = "samsung,exynos4210-pd";
	41	reg = <0x10044060 0x20>;
	42	clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
	43	<&clock CLK_MOUT_USER_ACLK333>;
	44	clock-names = "oscclk", "pclk0", "clk0";
a4a8c2c4	45	#power-domain-cells = <0>;
c760569d P	46	};
c760569d P	47
a4a8c2c4 TF	48	See Documentation/devicetree/bindings/power/power_domain.txt for description
a4a8c2c4 TF	49	of consumer-side bindings.