[deliverable/linux.git] / Documentation / devicetree / bindings / arm / gic-v3.txt

* ARM Generic Interrupt Controller, version 3

AArch64 SMP cores are often associated with a GICv3, providing Private
Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
Software Generated Interrupts (SGI), and Locality-specific Peripheral
Interrupts (LPI).

Main node required properties:

- compatible : should at least contain  "arm,gic-v3".
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
  interrupt source. Must be a single cell with a value of at least 3.

  The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
  interrupts. Other values are reserved for future use.

  The 2nd cell contains the interrupt number for the interrupt type.
  SPI interrupts are in the range [0-987]. PPI interrupts are in the
  range [0-15].

  The 3rd cell is the flags, encoded as follows:
	bits[3:0] trigger type and level flags.
		1 = edge triggered
		4 = level triggered

  Cells 4 and beyond are reserved for future use. When the 1st cell
  has a value of 0 or 1, cells 4 and beyond act as padding, and may be
  ignored. It is recommended that padding cells have a value of 0.

- reg : Specifies base physical address(s) and size of the GIC
  registers, in the following order:
  - GIC Distributor interface (GICD)
  - GIC Redistributors (GICR), one range per redistributor region
  - GIC CPU interface (GICC)
  - GIC Hypervisor interface (GICH)
  - GIC Virtual CPU interface (GICV)

  GICC, GICH and GICV are optional.

- interrupts : Interrupt source of the VGIC maintenance interrupt.

Optional

- redistributor-stride : If using padding pages, specifies the stride
  of consecutive redistributors. Must be a multiple of 64kB.

- #redistributor-regions: The number of independent contiguous regions
  occupied by the redistributors. Required if more than one such
  region is present.

Sub-nodes:

GICv3 has one or more Interrupt Translation Services (ITS) that are
used to route Message Signalled Interrupts (MSI) to the CPUs.

These nodes must have the following properties:
- compatible : Should at least contain  "arm,gic-v3-its".
- msi-controller : Boolean property. Identifies the node as an MSI controller
- reg: Specifies the base physical address and size of the ITS
  registers.

The main GIC node must contain the appropriate #address-cells,
#size-cells and ranges properties for the reg property of all ITS
nodes.

Examples:

	gic: interrupt-controller@2cf00000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		interrupt-controller;
		reg = <0x0 0x2f000000 0 0x10000>,	// GICD
		      <0x0 0x2f100000 0 0x200000>,	// GICR
		      <0x0 0x2c000000 0 0x2000>,	// GICC
		      <0x0 0x2c010000 0 0x2000>,	// GICH
		      <0x0 0x2c020000 0 0x2000>;	// GICV
		interrupts = <1 9 4>;

		gic-its@2c200000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			reg = <0x0 0x2c200000 0 0x200000>;
		};
	};

	gic: interrupt-controller@2c010000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		interrupt-controller;
		redistributor-stride = <0x0 0x40000>;	// 256kB stride
		#redistributor-regions = <2>;
		reg = <0x0 0x2c010000 0 0x10000>,	// GICD
		      <0x0 0x2d000000 0 0x800000>,	// GICR 1: CPUs 0-31
		      <0x0 0x2e000000 0 0x800000>;	// GICR 2: CPUs 32-63
		      <0x0 0x2c040000 0 0x2000>,	// GICC
		      <0x0 0x2c060000 0 0x2000>,	// GICH
		      <0x0 0x2c080000 0 0x2000>;	// GICV
		interrupts = <1 9 4>;

		gic-its@2c200000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			reg = <0x0 0x2c200000 0 0x200000>;
		};

		gic-its@2c400000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			reg = <0x0 0x2c400000 0 0x200000>;
		};
	};
Commit	Line	Data
96f68023 MZ	1	* ARM Generic Interrupt Controller, version 3
	2
	3	AArch64 SMP cores are often associated with a GICv3, providing Private
	4	Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
	5	Software Generated Interrupts (SGI), and Locality-specific Peripheral
	6	Interrupts (LPI).
	7
	8	Main node required properties:
	9
	10	- compatible : should at least contain "arm,gic-v3".
	11	- interrupt-controller : Identifies the node as an interrupt controller
	12	- #interrupt-cells : Specifies the number of cells needed to encode an
	13	interrupt source. Must be a single cell with a value of at least 3.
	14
	15	The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
	16	interrupts. Other values are reserved for future use.
	17
	18	The 2nd cell contains the interrupt number for the interrupt type.
	19	SPI interrupts are in the range [0-987]. PPI interrupts are in the
	20	range [0-15].
	21
	22	The 3rd cell is the flags, encoded as follows:
	23	bits[3:0] trigger type and level flags.
	24	1 = edge triggered
	25	4 = level triggered
	26
	27	Cells 4 and beyond are reserved for future use. When the 1st cell
	28	has a value of 0 or 1, cells 4 and beyond act as padding, and may be
	29	ignored. It is recommended that padding cells have a value of 0.
	30
	31	- reg : Specifies base physical address(s) and size of the GIC
	32	registers, in the following order:
	33	- GIC Distributor interface (GICD)
	34	- GIC Redistributors (GICR), one range per redistributor region
	35	- GIC CPU interface (GICC)
	36	- GIC Hypervisor interface (GICH)
	37	- GIC Virtual CPU interface (GICV)
	38
	39	GICC, GICH and GICV are optional.
	40
	41	- interrupts : Interrupt source of the VGIC maintenance interrupt.
	42
	43	Optional
	44
	45	- redistributor-stride : If using padding pages, specifies the stride
	46	of consecutive redistributors. Must be a multiple of 64kB.
	47
	48	- #redistributor-regions: The number of independent contiguous regions
	49	occupied by the redistributors. Required if more than one such
	50	region is present.
	51
b3a92e2c MZ	52	Sub-nodes:
	53
	54	GICv3 has one or more Interrupt Translation Services (ITS) that are
	55	used to route Message Signalled Interrupts (MSI) to the CPUs.
	56
	57	These nodes must have the following properties:
	58	- compatible : Should at least contain "arm,gic-v3-its".
	59	- msi-controller : Boolean property. Identifies the node as an MSI controller
	60	- reg: Specifies the base physical address and size of the ITS
	61	registers.
	62
	63	The main GIC node must contain the appropriate #address-cells,
	64	#size-cells and ranges properties for the reg property of all ITS
	65	nodes.
	66
96f68023 MZ	67	Examples:
	68
	69	gic: interrupt-controller@2cf00000 {
	70	compatible = "arm,gic-v3";
	71	#interrupt-cells = <3>;
b3a92e2c MZ	72	#address-cells = <2>;
	73	#size-cells = <2>;
	74	ranges;
96f68023 MZ	75	interrupt-controller;
	76	reg = <0x0 0x2f000000 0 0x10000>, // GICD
	77	<0x0 0x2f100000 0 0x200000>, // GICR
	78	<0x0 0x2c000000 0 0x2000>, // GICC
	79	<0x0 0x2c010000 0 0x2000>, // GICH
	80	<0x0 0x2c020000 0 0x2000>; // GICV
	81	interrupts = <1 9 4>;
b3a92e2c MZ	82
	83	gic-its@2c200000 {
	84	compatible = "arm,gic-v3-its";
	85	msi-controller;
	86	reg = <0x0 0x2c200000 0 0x200000>;
	87	};
96f68023 MZ	88	};
	89
	90	gic: interrupt-controller@2c010000 {
	91	compatible = "arm,gic-v3";
	92	#interrupt-cells = <3>;
b3a92e2c MZ	93	#address-cells = <2>;
	94	#size-cells = <2>;
	95	ranges;
96f68023 MZ	96	interrupt-controller;
	97	redistributor-stride = <0x0 0x40000>; // 256kB stride
	98	#redistributor-regions = <2>;
	99	reg = <0x0 0x2c010000 0 0x10000>, // GICD
	100	<0x0 0x2d000000 0 0x800000>, // GICR 1: CPUs 0-31
	101	<0x0 0x2e000000 0 0x800000>; // GICR 2: CPUs 32-63
	102	<0x0 0x2c040000 0 0x2000>, // GICC
	103	<0x0 0x2c060000 0 0x2000>, // GICH
	104	<0x0 0x2c080000 0 0x2000>; // GICV
	105	interrupts = <1 9 4>;
b3a92e2c MZ	106
	107	gic-its@2c200000 {
	108	compatible = "arm,gic-v3-its";
	109	msi-controller;
	110	reg = <0x0 0x2c200000 0 0x200000>;
	111	};
	112
	113	gic-its@2c400000 {
	114	compatible = "arm,gic-v3-its";
	115	msi-controller;
	116	reg = <0x0 0x2c400000 0 0x200000>;
	117	};
96f68023	118	};