Commit | Line | Data |
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b3f7ed03 RH |
1 | * ARM Generic Interrupt Controller |
2 | ||
3 | ARM SMP cores are often associated with a GIC, providing per processor | |
4 | interrupts (PPI), shared processor interrupts (SPI) and software | |
5 | generated interrupts (SGI). | |
6 | ||
7 | Primary GIC is attached directly to the CPU and typically has PPIs and SGIs. | |
8 | Secondary GICs are cascaded into the upward interrupt controller and do not | |
9 | have PPIs or SGIs. | |
10 | ||
11 | Main node required properties: | |
12 | ||
13 | - compatible : should be one of: | |
3ab72f91 | 14 | "arm,gic-400" |
0a68214b | 15 | "arm,cortex-a15-gic" |
b3f7ed03 | 16 | "arm,cortex-a9-gic" |
0a68214b | 17 | "arm,cortex-a7-gic" |
b3f7ed03 RH |
18 | "arm,arm11mp-gic" |
19 | - interrupt-controller : Identifies the node as an interrupt controller | |
20 | - #interrupt-cells : Specifies the number of cells needed to encode an | |
21 | interrupt source. The type shall be a <u32> and the value shall be 3. | |
22 | ||
23 | The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI | |
24 | interrupts. | |
25 | ||
26 | The 2nd cell contains the interrupt number for the interrupt type. | |
27 | SPI interrupts are in the range [0-987]. PPI interrupts are in the | |
28 | range [0-15]. | |
29 | ||
30 | The 3rd cell is the flags, encoded as follows: | |
31 | bits[3:0] trigger type and level flags. | |
32 | 1 = low-to-high edge triggered | |
33 | 2 = high-to-low edge triggered | |
34 | 4 = active high level-sensitive | |
35 | 8 = active low level-sensitive | |
36 | bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of | |
37 | the 8 possible cpus attached to the GIC. A bit set to '1' indicated | |
38 | the interrupt is wired to that CPU. Only valid for PPI interrupts. | |
39 | ||
40 | - reg : Specifies base physical address(s) and size of the GIC registers. The | |
41 | first region is the GIC distributor register base and size. The 2nd region is | |
42 | the GIC cpu interface register base and size. | |
43 | ||
44 | Optional | |
0a68214b | 45 | - interrupts : Interrupt source of the parent interrupt controller on |
f21ccfa0 | 46 | secondary GICs, or VGIC maintenance interrupt on primary GIC (see |
0a68214b | 47 | below). |
b3f7ed03 | 48 | |
db0d4db2 MZ |
49 | - cpu-offset : per-cpu offset within the distributor and cpu interface |
50 | regions, used when the GIC doesn't have banked registers. The offset is | |
51 | cpu-offset * cpu-nr. | |
52 | ||
006e983b S |
53 | - arm,routable-irqs : Total number of gic irq inputs which are not directly |
54 | connected from the peripherals, but are routed dynamically | |
55 | by a crossbar/multiplexer preceding the GIC. The GIC irq | |
56 | input line is assigned dynamically when the corresponding | |
57 | peripheral's crossbar line is mapped. | |
b3f7ed03 RH |
58 | Example: |
59 | ||
60 | intc: interrupt-controller@fff11000 { | |
61 | compatible = "arm,cortex-a9-gic"; | |
62 | #interrupt-cells = <3>; | |
63 | #address-cells = <1>; | |
64 | interrupt-controller; | |
006e983b | 65 | arm,routable-irqs = <160>; |
b3f7ed03 RH |
66 | reg = <0xfff11000 0x1000>, |
67 | <0xfff10100 0x100>; | |
68 | }; | |
69 | ||
0a68214b MZ |
70 | |
71 | * GIC virtualization extensions (VGIC) | |
72 | ||
73 | For ARM cores that support the virtualization extensions, additional | |
74 | properties must be described (they only exist if the GIC is the | |
75 | primary interrupt controller). | |
76 | ||
77 | Required properties: | |
78 | ||
79 | - reg : Additional regions specifying the base physical address and | |
80 | size of the VGIC registers. The first additional region is the GIC | |
81 | virtual interface control register base and size. The 2nd additional | |
82 | region is the GIC virtual cpu interface register base and size. | |
83 | ||
f21ccfa0 | 84 | - interrupts : VGIC maintenance interrupt. |
0a68214b MZ |
85 | |
86 | Example: | |
87 | ||
88 | interrupt-controller@2c001000 { | |
89 | compatible = "arm,cortex-a15-gic"; | |
90 | #interrupt-cells = <3>; | |
91 | interrupt-controller; | |
92 | reg = <0x2c001000 0x1000>, | |
93 | <0x2c002000 0x1000>, | |
94 | <0x2c004000 0x2000>, | |
95 | <0x2c006000 0x2000>; | |
96 | interrupts = <1 9 0xf04>; | |
97 | }; |