Commit | Line | Data |
---|---|---|
c1b40e44 SM |
1 | |
2 | * ARM Global Timer | |
3 | Cortex-A9 are often associated with a per-core Global timer. | |
4 | ||
5 | ** Timer node required properties: | |
6 | ||
10b1f231 ML |
7 | - compatible : should contain |
8 | * "arm,cortex-a5-global-timer" for Cortex-A5 global timers. | |
9 | * "arm,cortex-a9-global-timer" for Cortex-A9 global | |
10 | timers or any compatible implementation. Note: driver | |
11 | supports versions r2p0 and above. | |
c1b40e44 SM |
12 | |
13 | - interrupts : One interrupt to each core | |
14 | ||
15 | - reg : Specify the base address and the size of the GT timer | |
16 | register window. | |
17 | ||
18 | - clocks : Should be phandle to a clock. | |
19 | ||
20 | Example: | |
21 | ||
22 | timer@2c000600 { | |
23 | compatible = "arm,cortex-a9-global-timer"; | |
24 | reg = <0x2c000600 0x20>; | |
25 | interrupts = <1 13 0xf01>; | |
26 | clocks = <&arm_periph_clk>; | |
27 | }; |