Commit | Line | Data |
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8c369264 RH |
1 | * ARM L2 Cache Controller |
2 | ||
3 | ARM cores often have a separate level 2 cache controller. There are various | |
4 | implementations of the L2 cache controller with compatible programming models. | |
f3354ab6 LW |
5 | Some of the properties that are just prefixed "cache-*" are taken from section |
6 | 3.7.3 of the ePAPR v1.1 specification which can be found at: | |
7 | https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf | |
8 | ||
8c369264 RH |
9 | The ARM L2 cache representation in the device tree should be done as follows: |
10 | ||
11 | Required properties: | |
12 | ||
13 | - compatible : should be one of: | |
e68f31f4 SH |
14 | "arm,pl310-cache" |
15 | "arm,l220-cache" | |
16 | "arm,l210-cache" | |
17 | "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache" | |
18 | "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an | |
19 | offset needs to be added to the address before passing down to the L2 | |
20 | cache controller | |
21 | "marvell,aurora-system-cache": Marvell Controller designed to be | |
3ee11aef GC |
22 | compatible with the ARM one, with system cache mode (meaning |
23 | maintenance operations on L1 are broadcasted to the L2 and L2 | |
24 | performs the same operation). | |
e68f31f4 SH |
25 | "marvell,aurora-outer-cache": Marvell Controller designed to be |
26 | compatible with the ARM one with outer cache mode. | |
27 | "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible | |
28 | with arm,pl310-cache controller. | |
8c369264 RH |
29 | - cache-unified : Specifies the cache is a unified cache. |
30 | - cache-level : Should be set to 2 for a level 2 cache. | |
31 | - reg : Physical base address and size of cache controller's memory mapped | |
32 | registers. | |
33 | ||
34 | Optional properties: | |
35 | ||
36 | - arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of | |
37 | read, write and setup latencies. Minimum valid values are 1. Controllers | |
38 | without setup latency control should use a value of 0. | |
39 | - arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of | |
40 | read, write and setup latencies. Controllers without setup latency control | |
41 | should use 0. Controllers without separate read and write Tag RAM latency | |
42 | values should only use the first cell. | |
43 | - arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell. | |
44 | - arm,filter-ranges : <start length> Starting address and length of window to | |
45 | filter. Addresses in the filter window are directed to the M1 port. Other | |
46 | addresses will go to the M0 port. | |
98ea2dba TP |
47 | - arm,io-coherent : indicates that the system is operating in an hardware |
48 | I/O coherent mode. Valid only when the arm,pl310-cache compatible | |
49 | string is used. | |
8d4e652d | 50 | - interrupts : 1 combined interrupt. |
f3354ab6 LW |
51 | - cache-size : specifies the size in bytes of the cache |
52 | - cache-sets : specifies the number of associativity sets of the cache | |
53 | - cache-block-size : specifies the size in bytes of a cache block | |
54 | - cache-line-size : specifies the size in bytes of a line in the cache, | |
55 | if this is not specified, the line size is assumed to be equal to the | |
56 | cache block size | |
3ee11aef GC |
57 | - cache-id-part: cache id part number to be used if it is not present |
58 | on hardware | |
59 | - wt-override: If present then L2 is forced to Write through mode | |
cf0681ca TF |
60 | - arm,double-linefill : Override double linefill enable setting. Enable if |
61 | non-zero, disable if zero. | |
62 | - arm,double-linefill-incr : Override double linefill on INCR read. Enable | |
63 | if non-zero, disable if zero. | |
64 | - arm,double-linefill-wrap : Override double linefill on WRAP read. Enable | |
65 | if non-zero, disable if zero. | |
66 | - arm,prefetch-drop : Override prefetch drop enable setting. Enable if non-zero, | |
67 | disable if zero. | |
68 | - arm,prefetch-offset : Override prefetch offset value. Valid values are | |
69 | 0-7, 15, 23, and 31. | |
ec3bd0e6 HM |
70 | - prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1> |
71 | (forcibly enable), property absent (retain settings set by firmware) | |
72 | - prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable), | |
73 | <1> (forcibly enable), property absent (retain settings set by | |
74 | firmware) | |
8c369264 RH |
75 | |
76 | Example: | |
77 | ||
78 | L2: cache-controller { | |
79 | compatible = "arm,pl310-cache"; | |
80 | reg = <0xfff12000 0x1000>; | |
81 | arm,data-latency = <1 1 1>; | |
82 | arm,tag-latency = <2 2 2>; | |
20663060 | 83 | arm,filter-ranges = <0x80000000 0x8000000>; |
8c369264 RH |
84 | cache-unified; |
85 | cache-level = <2>; | |
8d4e652d | 86 | interrupts = <45>; |
8c369264 | 87 | }; |