Commit | Line | Data |
---|---|---|
f5c42271 RS |
1 | * NXP LPC32xx Main Interrupt Controller |
2 | (MIC, including SIC1 and SIC2 secondary controllers) | |
3 | ||
4 | Required properties: | |
5 | - compatible: Should be "nxp,lpc3220-mic" | |
6 | - interrupt-controller: Identifies the node as an interrupt controller. | |
7 | - interrupt-parent: Empty for the interrupt controller itself | |
8 | - #interrupt-cells: The number of cells to define the interrupts. Should be 2. | |
9 | The first cell is the IRQ number | |
10 | The second cell is used to specify mode: | |
11 | 1 = low-to-high edge triggered | |
12 | 2 = high-to-low edge triggered | |
13 | 4 = active high level-sensitive | |
14 | 8 = active low level-sensitive | |
15 | Default for internal sources should be set to 4 (active high). | |
16 | - reg: Should contain MIC registers location and length | |
17 | ||
18 | Examples: | |
19 | /* | |
20 | * MIC | |
21 | */ | |
22 | mic: interrupt-controller@40008000 { | |
23 | compatible = "nxp,lpc3220-mic"; | |
24 | interrupt-controller; | |
25 | interrupt-parent; | |
26 | #interrupt-cells = <2>; | |
27 | reg = <0x40008000 0xC000>; | |
28 | }; | |
29 | ||
30 | /* | |
31 | * ADC | |
32 | */ | |
33 | adc@40048000 { | |
34 | compatible = "nxp,lpc3220-adc"; | |
35 | reg = <0x40048000 0x1000>; | |
36 | interrupt-parent = <&mic>; | |
37 | interrupts = <39 4>; | |
38 | }; |