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2440946c SH |
1 | Marvell Berlin SoC Family Device Tree Bindings |
2 | --------------------------------------------------------------- | |
3 | ||
f07b4e49 AT |
4 | Work in progress statement: |
5 | ||
6 | Device tree files and bindings applying to Marvell Berlin SoCs and boards are | |
7 | considered "unstable". Any Marvell Berlin device tree binding may change at any | |
8 | time. Be sure to use a device tree binary and a kernel image generated from the | |
9 | same source tree. | |
10 | ||
11 | Please refer to Documentation/devicetree/bindings/ABI.txt for a definition of a | |
12 | stable binding/ABI. | |
13 | ||
14 | --------------------------------------------------------------- | |
15 | ||
2440946c SH |
16 | Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500 |
17 | shall have the following properties: | |
18 | ||
19 | * Required root node properties: | |
20 | compatible: must contain "marvell,berlin" | |
21 | ||
22 | In addition, the above compatible shall be extended with the specific | |
23 | SoC and board used. Currently known SoC compatibles are: | |
24 | "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100), | |
25 | "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005) | |
26 | "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????) | |
374ddcbf | 27 | "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114) |
2440946c SH |
28 | "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????) |
29 | ||
30 | * Example: | |
31 | ||
32 | / { | |
33 | model = "Sony NSZ-GS7"; | |
34 | compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin"; | |
35 | ||
36 | ... | |
37 | } | |
55a4b07a | 38 | |
9ab5fb8a AT |
39 | * Marvell Berlin CPU control bindings |
40 | ||
41 | CPU control register allows various operations on CPUs, like resetting them | |
42 | independently. | |
43 | ||
44 | Required properties: | |
45 | - compatible: should be "marvell,berlin-cpu-ctrl" | |
46 | - reg: address and length of the register set | |
47 | ||
48 | Example: | |
49 | ||
50 | cpu-ctrl@f7dd0000 { | |
51 | compatible = "marvell,berlin-cpu-ctrl"; | |
52 | reg = <0xf7dd0000 0x10000>; | |
53 | }; | |
54 | ||
55a4b07a SH |
55 | * Marvell Berlin2 chip control binding |
56 | ||
57 | Marvell Berlin SoCs have a chip control register set providing several | |
58 | individual registers dealing with pinmux, padmux, clock, reset, and secondary | |
59 | CPU boot address. Unfortunately, the individual registers are spread among the | |
60 | chip control registers, so there should be a single DT node only providing the | |
61 | different functions which are described below. | |
62 | ||
63 | Required properties: | |
7c90a5a9 | 64 | - compatible: |
576efe38 | 65 | * the first and second values must be: |
7c90a5a9 | 66 | "simple-mfd", "syscon" |
55a4b07a SH |
67 | - reg: address and length of following register sets for |
68 | BG2/BG2CD: chip control register set | |
69 | BG2Q: chip control register set and cpu pll registers | |
70 | ||
e9673a75 AT |
71 | * Marvell Berlin2 system control binding |
72 | ||
73 | Marvell Berlin SoCs have a system control register set providing several | |
74 | individual registers dealing with pinmux, padmux, and reset. | |
75 | ||
76 | Required properties: | |
7c90a5a9 | 77 | - compatible: |
576efe38 | 78 | * the first and second values must be: |
7c90a5a9 | 79 | "simple-mfd", "syscon" |
e9673a75 AT |
80 | - reg: address and length of the system control register set |
81 | ||
55a4b07a SH |
82 | Example: |
83 | ||
84 | chip: chip-control@ea0000 { | |
576efe38 | 85 | compatible = "simple-mfd", "syscon"; |
55a4b07a | 86 | reg = <0xea0000 0x400>; |
c1f86f2f AT |
87 | |
88 | /* sub-device nodes */ | |
e9673a75 AT |
89 | }; |
90 | ||
91 | sysctrl: system-controller@d000 { | |
576efe38 | 92 | compatible = "simple-mfd", "syscon"; |
e9673a75 | 93 | reg = <0xd000 0x100>; |
c1f86f2f AT |
94 | |
95 | /* sub-device nodes */ | |
55a4b07a | 96 | }; |