projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 7415b0b4 TK |
1 | OMAP Control Module bindings |
| 2 | ||
| 3 | Control Module contains miscellaneous features under it based on SoC type. | |
| 4 | Pincontrol is one common feature, and it has a specialized support | |
| 5 | described in [1]. Typically some clock nodes are also under control module. | |
| 6 | Syscon is used to share register level access to drivers external to | |
| 7 | control module driver itself. | |
| 8 | ||
| 9 | See [2] for documentation about clock/clockdomain nodes. | |
| 10 | ||
| 11 | [1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt | |
| 12 | [2] Documentation/devicetree/bindings/clock/ti/* | |
| 13 | ||
| 14 | Required properties: | |
| 15 | - compatible: Must be one of: | |
| 16 | "ti,am3-scm" | |
| 17 | "ti,am4-scm" | |
| 18 | "ti,dm814-scrm" | |
| 19 | "ti,dm816-scrm" | |
| 20 | "ti,omap2-scm" | |
| 21 | "ti,omap3-scm" | |
| 22 | "ti,omap4-scm-core" | |
| 23 | "ti,omap4-scm-padconf-core" | |
| ed8509ed TK |
24 | "ti,omap5-scm-core" |
| 25 | "ti,omap5-scm-padconf-core" | |
| d919501f | 26 | "ti,dra7-scm-core" |
| 7415b0b4 TK |
27 | - reg: Contains Control Module register address range |
| 28 | (base address and length) | |
| 29 | ||
| 30 | Optional properties: | |
| 31 | - clocks: clocks for this module | |
| 32 | - clockdomains: clockdomains for this module | |
| 33 | ||
| 34 | Examples: | |
| 35 | ||
| 36 | scm: scm@2000 { | |
| 37 | compatible = "ti,omap3-scm", "simple-bus"; | |
| 38 | reg = <0x2000 0x2000>; | |
| 39 | #address-cells = <1>; | |
| 40 | #size-cells = <1>; | |
| 41 | ranges = <0 0x2000 0x2000>; | |
| 42 | ||
| 43 | omap3_pmx_core: pinmux@30 { | |
| 44 | compatible = "ti,omap3-padconf", | |
| 45 | "pinctrl-single"; | |
| 46 | reg = <0x30 0x230>; | |
| 47 | #address-cells = <1>; | |
| 48 | #size-cells = <0>; | |
| 49 | #interrupt-cells = <1>; | |
| 50 | interrupt-controller; | |
| 51 | pinctrl-single,register-width = <16>; | |
| 52 | pinctrl-single,function-mask = <0xff1f>; | |
| 53 | }; | |
| 54 | ||
| 55 | scm_conf: scm_conf@270 { | |
| 56 | compatible = "syscon"; | |
| 57 | reg = <0x270 0x330>; | |
| 58 | #address-cells = <1>; | |
| 59 | #size-cells = <1>; | |
| 60 | ||
| 61 | scm_clocks: clocks { | |
| 62 | #address-cells = <1>; | |
| 63 | #size-cells = <0>; | |
| 64 | }; | |
| 65 | }; | |
| 66 | ||
| 67 | scm_clockdomains: clockdomains { | |
| 68 | }; | |
| 69 | } | |
| 70 | ||
| 71 | &scm_clocks { | |
| 72 | mcbsp5_mux_fck: mcbsp5_mux_fck { | |
| 73 | #clock-cells = <0>; | |
| 74 | compatible = "ti,composite-mux-clock"; | |
| 75 | clocks = <&core_96m_fck>, <&mcbsp_clks>; | |
| 76 | ti,bit-shift = <4>; | |
| 77 | reg = <0x02d8>; | |
| 78 | }; | |
| 79 | }; |