[deliverable/linux.git] / Documentation / devicetree / bindings / arm / pmu.txt

* ARM Performance Monitor Units

ARM cores often have a PMU for counting cpu and cache events like cache misses
and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
representation in the device tree should be done as under:-

Required properties:

- compatible : should be one of
	"apm,potenza-pmu"
	"arm,armv8-pmuv3"
	"arm,cortex-a72-pmu"
	"arm,cortex-a57-pmu"
	"arm,cortex-a53-pmu"
	"arm,cortex-a17-pmu"
	"arm,cortex-a15-pmu"
	"arm,cortex-a12-pmu"
	"arm,cortex-a9-pmu"
	"arm,cortex-a8-pmu"
	"arm,cortex-a7-pmu"
	"arm,cortex-a5-pmu"
	"arm,arm11mpcore-pmu"
	"arm,arm1176-pmu"
	"arm,arm1136-pmu"
	"brcm,vulcan-pmu"
	"cavium,thunder-pmu"
	"qcom,scorpion-pmu"
	"qcom,scorpion-mp-pmu"
	"qcom,krait-pmu"
- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
               interrupt (PPI) then 1 interrupt should be specified.

Optional properties:

- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU
                       nodes corresponding directly to the affinity of
		       the SPIs listed in the interrupts property.

                       When using a PPI, specifies a list of phandles to CPU
		       nodes corresponding to the set of CPUs which have
		       a PMU of this type signalling the PPI listed in the
		       interrupts property.

                       This property should be present when there is more than
		       a single SPI.


- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
                     events.

- secure-reg-access : Indicates that the ARMv7 Secure Debug Enable Register
		      (SDER) is accessible. This will cause the driver to do
		      any setup required that is only possible in ARMv7 secure
		      state. If not present the ARMv7 SDER will not be touched,
		      which means the PMU may fail to operate unless external
		      code (bootloader or security monitor) has performed the
		      appropriate initialisation. Note that this property is
		      not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
		      in Non-secure state.

Example:

pmu {
        compatible = "arm,cortex-a9-pmu";
        interrupts = <100 101>;
};
Commit	Line	Data
e73c34c3 MR	1	* ARM Performance Monitor Units
	2
	3	ARM cores often have a PMU for counting cpu and cache events like cache misses
	4	and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
	5	representation in the device tree should be done as under:-
	6
	7	Required properties:
	8
	9	- compatible : should be one of
51f1e4a0	10	"apm,potenza-pmu"
f04bda90	11	"arm,armv8-pmuv3"
5d7ee877	12	"arm,cortex-a72-pmu"
aae881ad GU	13	"arm,cortex-a57-pmu"
aae881ad GU	14	"arm,cortex-a53-pmu"
03eff46c	15	"arm,cortex-a17-pmu"
50243efd	16	"arm,cortex-a15-pmu"
8e781f65	17	"arm,cortex-a12-pmu"
e73c34c3 MR	18	"arm,cortex-a9-pmu"
e73c34c3 MR	19	"arm,cortex-a8-pmu"
50243efd WD	20	"arm,cortex-a7-pmu"
	21	"arm,cortex-a5-pmu"
	22	"arm,arm11mpcore-pmu"
e73c34c3 MR	23	"arm,arm1176-pmu"
e73c34c3 MR	24	"arm,arm1136-pmu"
ce29daf5 AK	25	"brcm,vulcan-pmu"
ce29daf5 AK	26	"cavium,thunder-pmu"
341e42c4 SB	27	"qcom,scorpion-pmu"
341e42c4 SB	28	"qcom,scorpion-mp-pmu"
d84c4783 SB	29	"qcom,krait-pmu"
	30	- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
	31	interrupt (PPI) then 1 interrupt should be specified.
	32
	33	Optional properties:
	34
b6c084d7 WD	35	- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU
b6c084d7 WD	36	nodes corresponding directly to the affinity of
71bbf038 WD	37	the SPIs listed in the interrupts property.
71bbf038 WD	38
b6c084d7 WD	39	When using a PPI, specifies a list of phandles to CPU
	40	nodes corresponding to the set of CPUs which have
	41	a PMU of this type signalling the PPI listed in the
	42	interrupts property.
	43
	44	This property should be present when there is more than
71bbf038 WD	45	a single SPI.
71bbf038 WD	46
b6c084d7	47
d84c4783 SB	48	- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
d84c4783 SB	49	events.
e73c34c3	50
8d1a0ae7 MF	51	- secure-reg-access : Indicates that the ARMv7 Secure Debug Enable Register
	52	(SDER) is accessible. This will cause the driver to do
	53	any setup required that is only possible in ARMv7 secure
	54	state. If not present the ARMv7 SDER will not be touched,
	55	which means the PMU may fail to operate unless external
	56	code (bootloader or security monitor) has performed the
	57	appropriate initialisation. Note that this property is
	58	not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
	59	in Non-secure state.
	60
e73c34c3 MR	61	Example:
	62
	63	pmu {
	64	compatible = "arm,cortex-a9-pmu";
	65	interrupts = <100 101>;
	66	};