[deliverable/linux.git] / Documentation / devicetree / bindings / arm / pmu.txt

* ARM Performance Monitor Units

ARM cores often have a PMU for counting cpu and cache events like cache misses
and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
representation in the device tree should be done as under:-

Required properties:

- compatible : should be one of
	"arm,cortex-a15-pmu"
	"arm,cortex-a9-pmu"
	"arm,cortex-a8-pmu"
	"arm,cortex-a7-pmu"
	"arm,cortex-a5-pmu"
	"arm,arm11mpcore-pmu"
	"arm,arm1176-pmu"
	"arm,arm1136-pmu"
- interrupts : 1 combined interrupt or 1 per core.

Example:

pmu {
        compatible = "arm,cortex-a9-pmu";
        interrupts = <100 101>;
};
Commit	Line	Data
e73c34c3 MR	1	* ARM Performance Monitor Units
	2
	3	ARM cores often have a PMU for counting cpu and cache events like cache misses
	4	and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
	5	representation in the device tree should be done as under:-
	6
	7	Required properties:
	8
	9	- compatible : should be one of
50243efd	10	"arm,cortex-a15-pmu"
e73c34c3 MR	11	"arm,cortex-a9-pmu"
e73c34c3 MR	12	"arm,cortex-a8-pmu"
50243efd WD	13	"arm,cortex-a7-pmu"
	14	"arm,cortex-a5-pmu"
	15	"arm,arm11mpcore-pmu"
e73c34c3 MR	16	"arm,arm1176-pmu"
	17	"arm,arm1136-pmu"
	18	- interrupts : 1 combined interrupt or 1 per core.
	19
	20	Example:
	21
	22	pmu {
	23	compatible = "arm,cortex-a9-pmu";
	24	interrupts = <100 101>;
	25	};