Commit | Line | Data |
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af468109 HD |
1 | NVIDIA Tegra30 MC(Memory Controller) |
2 | ||
3 | Required properties: | |
4 | - compatible : "nvidia,tegra30-mc" | |
5 | - reg : Should contain 4 register ranges(address and length); see the | |
6 | example below. Note that the MC registers are interleaved with the | |
7 | SMMU registers, and hence must be represented as multiple ranges. | |
8 | - interrupts : Should contain MC General interrupt. | |
9 | ||
10 | Example: | |
eed6e344 | 11 | memory-controller { |
af468109 HD |
12 | compatible = "nvidia,tegra30-mc"; |
13 | reg = <0x7000f000 0x010 | |
14 | 0x7000f03c 0x1b4 | |
15 | 0x7000f200 0x028 | |
16 | 0x7000f284 0x17c>; | |
17 | interrupts = <0 77 0x04>; | |
18 | }; |