Commit | Line | Data |
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9bc15031 LW |
1 | * ARM Versatile FPGA interrupt controller |
2 | ||
3 | One or more FPGA IRQ controllers can be synthesized in an ARM reference board | |
4 | such as the Integrator or Versatile family. The output of these different | |
5 | controllers are OR:ed together and fed to the CPU tile's IRQ input. Each | |
6 | instance can handle up to 32 interrupts. | |
7 | ||
8 | Required properties: | |
9 | - compatible: "arm,versatile-fpga-irq" | |
10 | - interrupt-controller: Identifies the node as an interrupt controller | |
11 | - #interrupt-cells: The number of cells to define the interrupts. Must be 1 | |
12 | as the FPGA IRQ controller has no configuration options for interrupt | |
13 | sources. The cell is a u32 and defines the interrupt number. | |
14 | - reg: The register bank for the FPGA interrupt controller. | |
15 | - clear-mask: a u32 number representing the mask written to clear all IRQs | |
16 | on the controller at boot for example. | |
17 | - valid-mask: a u32 number representing a bit mask determining which of | |
18 | the interrupts are valid. Unconnected/unused lines are set to 0, and | |
19 | the system till not make it possible for devices to request these | |
20 | interrupts. | |
21 | ||
22 | Example: | |
23 | ||
24 | pic: pic@14000000 { | |
25 | compatible = "arm,versatile-fpga-irq"; | |
26 | #interrupt-cells = <1>; | |
27 | interrupt-controller; | |
28 | reg = <0x14000000 0x100>; | |
29 | clear-mask = <0xffffffff>; | |
30 | valid-mask = <0x003fffff>; | |
31 | }; | |
bdd272cb LW |
32 | |
33 | Optional properties: | |
34 | - interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ | |
35 | output is simply connected to the input of another IRQ controller, | |
36 | then the parent IRQ shall be specified in this property. |