Commit | Line | Data |
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f9b28ccb JI |
1 | * ARM Vectored Interrupt Controller |
2 | ||
3 | One or more Vectored Interrupt Controllers (VIC's) can be connected in an ARM | |
4 | system for interrupt routing. For multiple controllers they can either be | |
5 | nested or have the outputs wire-OR'd together. | |
6 | ||
7 | Required properties: | |
8 | ||
9 | - compatible : should be one of | |
10 | "arm,pl190-vic" | |
11 | "arm,pl192-vic" | |
12 | - interrupt-controller : Identifies the node as an interrupt controller | |
13 | - #interrupt-cells : The number of cells to define the interrupts. Must be 1 as | |
14 | the VIC has no configuration options for interrupt sources. The cell is a u32 | |
15 | and defines the interrupt number. | |
16 | - reg : The register bank for the VIC. | |
17 | ||
18 | Optional properties: | |
19 | ||
20 | - interrupts : Interrupt source for parent controllers if the VIC is nested. | |
81e9c179 TF |
21 | - valid-mask : A one cell big bit mask of valid interrupt sources. Each bit |
22 | represents single interrupt source, starting from source 0 at LSb and ending | |
23 | at source 31 at MSb. A bit that is set means that the source is wired and | |
24 | clear means otherwise. If unspecified, defaults to all valid. | |
25 | - valid-wakeup-mask : A one cell big bit mask of interrupt sources that can be | |
26 | configured as wake up source for the system. Order of bits is the same as for | |
27 | valid-mask property. A set bit means that this interrupt source can be | |
28 | configured as a wake up source for the system. If unspecied, defaults to all | |
29 | interrupt sources configurable as wake up sources. | |
f9b28ccb JI |
30 | |
31 | Example: | |
32 | ||
33 | vic0: interrupt-controller@60000 { | |
34 | compatible = "arm,pl192-vic"; | |
35 | interrupt-controller; | |
36 | #interrupt-cells = <1>; | |
37 | reg = <0x60000 0x1000>; | |
81e9c179 TF |
38 | |
39 | valid-mask = <0xffffff7f>; | |
40 | valid-wakeup-mask = <0x0000ff7f>; | |
f9b28ccb | 41 | }; |