[deliverable/linux.git] / Documentation / devicetree / bindings / ata / ahci-fsl-qoriq.txt

Binding for Freescale QorIQ AHCI SATA Controller

Required properties:
  - reg: Physical base address and size of the controller's register area.
  - compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
    chip could be ls1021a, ls2080a, ls1043a etc.
  - clocks: Input clock specifier. Refer to common clock bindings.
  - interrupts: Interrupt specifier. Refer to interrupt binding.

Optional properties:
  - dma-coherent: Enable AHCI coherent DMA operation.
  - reg-names: register area names when there are more than 1 register area.

Examples:
	sata@3200000 {
		compatible = "fsl,ls1021a-ahci";
		reg = <0x0 0x3200000 0x0 0x10000>;
		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&platform_clk 1>;
		dma-coherent;
	};
Commit	Line	Data
437dd8c3 TY	1	Binding for Freescale QorIQ AHCI SATA Controller
	2
	3	Required properties:
	4	- reg: Physical base address and size of the controller's register area.
	5	- compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
d19f9aaf	6	chip could be ls1021a, ls2080a, ls1043a etc.
437dd8c3 TY	7	- clocks: Input clock specifier. Refer to common clock bindings.
	8	- interrupts: Interrupt specifier. Refer to interrupt binding.
	9
	10	Optional properties:
d72c0f43 TY	11	- dma-coherent: Enable AHCI coherent DMA operation.
d72c0f43 TY	12	- reg-names: register area names when there are more than 1 register area.
437dd8c3 TY	13
	14	Examples:
	15	sata@3200000 {
	16	compatible = "fsl,ls1021a-ahci";
	17	reg = <0x0 0x3200000 0x0 0x10000>;
	18	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	19	clocks = <&platform_clk 1>;
	20	dma-coherent;
	21	};