Commit | Line | Data |
---|---|---|
e53c0772 FF |
1 | Broadcom GISB bus Arbiter controller |
2 | ||
3 | Required properties: | |
4 | ||
5 | - compatible: should be "brcm,gisb-arb" | |
6 | - reg: specifies the base physical address and size of the registers | |
7 | - interrupt-parent: specifies the phandle to the parent interrupt controller | |
8 | this arbiter gets interrupt line from | |
9 | - interrupts: specifies the two interrupts (timeout and TEA) to be used from | |
10 | the parent interrupt controller | |
11 | ||
12 | Optional properties: | |
13 | ||
14 | - brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB | |
15 | masters are valid at the system level | |
16 | - brcm,gisb-arb-master-names: string list of the litteral name of the GISB | |
17 | masters. Should match the number of bits set in brcm,gisb-master-mask and | |
18 | the order in which they appear | |
19 | ||
20 | Example: | |
21 | ||
22 | gisb-arb@f0400000 { | |
23 | compatible = "brcm,gisb-arb"; | |
24 | reg = <0xf0400000 0x800>; | |
25 | interrupts = <0>, <2>; | |
26 | interrupt-parent = <&sun_l2_intc>; | |
27 | ||
28 | brcm,gisb-arb-master-mask = <0x7>; | |
29 | brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0"; | |
30 | }; |