projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| bc6b1e7b DM |
1 | Device tree bindings for OMAP general purpose memory controllers (GPMC) |
| 2 | ||
| 3 | The actual devices are instantiated from the child nodes of a GPMC node. | |
| 4 | ||
| 5 | Required properties: | |
| 6 | ||
| 7 | - compatible: Should be set to one of the following: | |
| 8 | ||
| 9 | ti,omap2420-gpmc (omap2420) | |
| 10 | ti,omap2430-gpmc (omap2430) | |
| 11 | ti,omap3430-gpmc (omap3430 & omap3630) | |
| 12 | ti,omap4430-gpmc (omap4430 & omap4460 & omap543x) | |
| 13 | ti,am3352-gpmc (am335x devices) | |
| 14 | ||
| 15 | - reg: A resource specifier for the register space | |
| 16 | (see the example below) | |
| 17 | - ti,hwmods: Should be set to "ti,gpmc" until the DT transition is | |
| 18 | completed. | |
| 19 | - #address-cells: Must be set to 2 to allow memory address translation | |
| 20 | - #size-cells: Must be set to 1 to allow CS address passing | |
| 21 | - gpmc,num-cs: The maximum number of chip-select lines that controller | |
| 22 | can support. | |
| 23 | - gpmc,num-waitpins: The maximum number of wait pins that controller can | |
| 24 | support. | |
| 25 | - ranges: Must be set up to reflect the memory layout with four | |
| 26 | integer values for each chip-select line in use: | |
| 27 | ||
| 28 | <cs-number> 0 <physical address of mapping> <size> | |
| 29 | ||
| 30 | Currently, calculated values derived from the contents | |
| 31 | of the per-CS register GPMC_CONFIG7 (as set up by the | |
| 32 | bootloader) are used for the physical address decoding. | |
| 33 | As this will change in the future, filling correct | |
| 34 | values here is a requirement. | |
| 35 | ||
| 36 | Timing properties for child nodes. All are optional and default to 0. | |
| 37 | ||
| 38 | - gpmc,sync-clk: Minimum clock period for synchronous mode, in picoseconds | |
| 39 | ||
| 40 | Chip-select signal timings corresponding to GPMC_CONFIG2: | |
| 41 | - gpmc,cs-on: Assertion time | |
| 42 | - gpmc,cs-rd-off: Read deassertion time | |
| 43 | - gpmc,cs-wr-off: Write deassertion time | |
| 44 | ||
| 45 | ADV signal timings corresponding to GPMC_CONFIG3: | |
| 46 | - gpmc,adv-on: Assertion time | |
| 47 | - gpmc,adv-rd-off: Read deassertion time | |
| 48 | - gpmc,adv-wr-off: Write deassertion time | |
| 49 | ||
| 50 | WE signals timings corresponding to GPMC_CONFIG4: | |
| 51 | - gpmc,we-on: Assertion time | |
| 52 | - gpmc,we-off: Deassertion time | |
| 53 | ||
| 54 | OE signals timings corresponding to GPMC_CONFIG4: | |
| 55 | - gpmc,oe-on: Assertion time | |
| 56 | - gpmc,oe-off: Deassertion time | |
| 57 | ||
| 58 | Access time and cycle time timings corresponding to GPMC_CONFIG5: | |
| 59 | - gpmc,page-burst-access: Multiple access word delay | |
| 60 | - gpmc,access: Start-cycle to first data valid delay | |
| 61 | - gpmc,rd-cycle: Total read cycle time | |
| 62 | - gpmc,wr-cycle: Total write cycle time | |
| 63 | ||
| 64 | The following are only applicable to OMAP3+ and AM335x: | |
| 65 | - gpmc,wr-access | |
| 66 | - gpmc,wr-data-mux-bus | |
| 67 | ||
| 68 | ||
| 69 | Example for an AM33xx board: | |
| 70 | ||
| 71 | gpmc: gpmc@50000000 { | |
| 72 | compatible = "ti,am3352-gpmc"; | |
| 73 | ti,hwmods = "gpmc"; | |
| 74 | reg = <0x50000000 0x2000>; | |
| 75 | interrupts = <100>; | |
| 76 | ||
| 77 | gpmc,num-cs = <8>; | |
| 78 | gpmc,num-waitpins = <2>; | |
| 79 | #address-cells = <2>; | |
| 80 | #size-cells = <1>; | |
| 81 | ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */ | |
| 82 | ||
| 83 | /* child nodes go here */ | |
| 84 | }; |