Commit | Line | Data |
---|---|---|
b598b9f3 SG |
1 | * Clock bindings for Freescale i.MX28 |
2 | ||
3 | Required properties: | |
4 | - compatible: Should be "fsl,imx28-clkctrl" | |
5 | - reg: Address and length of the register set | |
6 | - #clock-cells: Should be <1> | |
7 | ||
8 | The clock consumer should specify the desired clock by having the clock | |
9 | ID in its "clocks" phandle cell. The following is a full list of i.MX28 | |
10 | clocks and IDs. | |
11 | ||
12 | Clock ID | |
13 | ------------------ | |
14 | ref_xtal 0 | |
15 | pll0 1 | |
16 | pll1 2 | |
17 | pll2 3 | |
18 | ref_cpu 4 | |
19 | ref_emi 5 | |
20 | ref_io0 6 | |
21 | ref_io1 7 | |
22 | ref_pix 8 | |
23 | ref_hsadc 9 | |
24 | ref_gpmi 10 | |
25 | saif0_sel 11 | |
26 | saif1_sel 12 | |
27 | gpmi_sel 13 | |
28 | ssp0_sel 14 | |
29 | ssp1_sel 15 | |
30 | ssp2_sel 16 | |
31 | ssp3_sel 17 | |
32 | emi_sel 18 | |
33 | etm_sel 19 | |
34 | lcdif_sel 20 | |
35 | cpu 21 | |
36 | ptp_sel 22 | |
37 | cpu_pll 23 | |
38 | cpu_xtal 24 | |
39 | hbus 25 | |
40 | xbus 26 | |
41 | ssp0_div 27 | |
42 | ssp1_div 28 | |
43 | ssp2_div 29 | |
44 | ssp3_div 30 | |
45 | gpmi_div 31 | |
46 | emi_pll 32 | |
47 | emi_xtal 33 | |
48 | lcdif_div 34 | |
49 | etm_div 35 | |
50 | ptp 36 | |
51 | saif0_div 37 | |
52 | saif1_div 38 | |
53 | clk32k_div 39 | |
54 | rtc 40 | |
55 | lradc 41 | |
56 | spdif_div 42 | |
57 | clk32k 43 | |
58 | pwm 44 | |
59 | uart 45 | |
60 | ssp0 46 | |
61 | ssp1 47 | |
62 | ssp2 48 | |
63 | ssp3 49 | |
64 | gpmi 50 | |
65 | spdif 51 | |
66 | emi 52 | |
67 | saif0 53 | |
68 | saif1 54 | |
69 | lcdif 55 | |
70 | etm 56 | |
71 | fec 57 | |
72 | can0 58 | |
73 | can1 59 | |
74 | usb0 60 | |
75 | usb1 61 | |
f5894539 FE |
76 | usb0_phy 62 |
77 | usb1_phy 63 | |
b598b9f3 SG |
78 | enet_out 64 |
79 | ||
80 | Examples: | |
81 | ||
82 | clks: clkctrl@80040000 { | |
83 | compatible = "fsl,imx28-clkctrl"; | |
84 | reg = <0x80040000 0x2000>; | |
85 | #clock-cells = <1>; | |
b598b9f3 SG |
86 | }; |
87 | ||
88 | auart0: serial@8006a000 { | |
89 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; | |
90 | reg = <0x8006a000 0x2000>; | |
91 | interrupts = <112 70 71>; | |
92 | clocks = <&clks 45>; | |
93 | status = "disabled"; | |
94 | }; |