Commit | Line | Data |
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c7bb4fc1 JJ |
1 | Device Tree Clock bindings for arch-moxart |
2 | ||
3 | This binding uses the common clock binding[1]. | |
4 | ||
5 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | |
6 | ||
7 | MOXA ART SoCs allow to determine PLL output and APB frequencies | |
8 | by reading registers holding multiplier and divisor information. | |
9 | ||
10 | ||
11 | PLL: | |
12 | ||
13 | Required properties: | |
14 | - compatible : Must be "moxa,moxart-pll-clock" | |
15 | - #clock-cells : Should be 0 | |
16 | - reg : Should contain registers location and length | |
17 | - clocks : Should contain phandle + clock-specifier for the parent clock | |
18 | ||
19 | Optional properties: | |
20 | - clock-output-names : Should contain clock name | |
21 | ||
22 | ||
23 | APB: | |
24 | ||
25 | Required properties: | |
26 | - compatible : Must be "moxa,moxart-apb-clock" | |
27 | - #clock-cells : Should be 0 | |
28 | - reg : Should contain registers location and length | |
29 | - clocks : Should contain phandle + clock-specifier for the parent clock | |
30 | ||
31 | Optional properties: | |
32 | - clock-output-names : Should contain clock name | |
33 | ||
34 | ||
35 | For example: | |
36 | ||
37 | clk_pll: clk_pll@98100000 { | |
38 | compatible = "moxa,moxart-pll-clock"; | |
39 | #clock-cells = <0>; | |
40 | reg = <0x98100000 0x34>; | |
41 | }; | |
42 | ||
43 | clk_apb: clk_apb@98100000 { | |
44 | compatible = "moxa,moxart-apb-clock"; | |
45 | #clock-cells = <0>; | |
46 | reg = <0x98100000 0x34>; | |
47 | clocks = <&clk_pll>; | |
48 | }; |