projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| c9c96ae2 PCC |
1 | Device Tree Clock bindins for CPU DVFS of Mediatek MT8173 SoC |
| 2 | ||
| 3 | Required properties: | |
| 4 | - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names. | |
| 5 | - clock-names: Should contain the following: | |
| 6 | "cpu" - The multiplexer for clock input of CPU cluster. | |
| 7 | "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock | |
| 8 | source (usually MAINPLL) when the original CPU PLL is under | |
| 9 | transition and not stable yet. | |
| 10 | Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for | |
| 11 | generic clock consumer properties. | |
| 12 | - proc-supply: Regulator for Vproc of CPU cluster. | |
| 13 | ||
| 14 | Optional properties: | |
| 15 | - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver | |
| 16 | needs to do "voltage tracking" to step by step scale up/down Vproc and | |
| 17 | Vsram to fit SoC specific needs. When absent, the voltage scaling | |
| 18 | flow is handled by hardware, hence no software "voltage tracking" is | |
| 19 | needed. | |
| 20 | ||
| 21 | Example: | |
| 22 | -------- | |
| 23 | cpu0: cpu@0 { | |
| 24 | device_type = "cpu"; | |
| 25 | compatible = "arm,cortex-a53"; | |
| 26 | reg = <0x000>; | |
| 27 | enable-method = "psci"; | |
| 28 | cpu-idle-states = <&CPU_SLEEP_0>; | |
| 29 | clocks = <&infracfg CLK_INFRA_CA53SEL>, | |
| 30 | <&apmixedsys CLK_APMIXED_MAINPLL>; | |
| 31 | clock-names = "cpu", "intermediate"; | |
| 32 | }; | |
| 33 | ||
| 34 | cpu1: cpu@1 { | |
| 35 | device_type = "cpu"; | |
| 36 | compatible = "arm,cortex-a53"; | |
| 37 | reg = <0x001>; | |
| 38 | enable-method = "psci"; | |
| 39 | cpu-idle-states = <&CPU_SLEEP_0>; | |
| 40 | clocks = <&infracfg CLK_INFRA_CA53SEL>, | |
| 41 | <&apmixedsys CLK_APMIXED_MAINPLL>; | |
| 42 | clock-names = "cpu", "intermediate"; | |
| 43 | }; | |
| 44 | ||
| 45 | cpu2: cpu@100 { | |
| 46 | device_type = "cpu"; | |
| 47 | compatible = "arm,cortex-a57"; | |
| 48 | reg = <0x100>; | |
| 49 | enable-method = "psci"; | |
| 50 | cpu-idle-states = <&CPU_SLEEP_0>; | |
| 51 | clocks = <&infracfg CLK_INFRA_CA57SEL>, | |
| 52 | <&apmixedsys CLK_APMIXED_MAINPLL>; | |
| 53 | clock-names = "cpu", "intermediate"; | |
| 54 | }; | |
| 55 | ||
| 56 | cpu3: cpu@101 { | |
| 57 | device_type = "cpu"; | |
| 58 | compatible = "arm,cortex-a57"; | |
| 59 | reg = <0x101>; | |
| 60 | enable-method = "psci"; | |
| 61 | cpu-idle-states = <&CPU_SLEEP_0>; | |
| 62 | clocks = <&infracfg CLK_INFRA_CA57SEL>, | |
| 63 | <&apmixedsys CLK_APMIXED_MAINPLL>; | |
| 64 | clock-names = "cpu", "intermediate"; | |
| 65 | }; | |
| 66 | ||
| 67 | &cpu0 { | |
| 68 | proc-supply = <&mt6397_vpca15_reg>; | |
| 69 | }; | |
| 70 | ||
| 71 | &cpu1 { | |
| 72 | proc-supply = <&mt6397_vpca15_reg>; | |
| 73 | }; | |
| 74 | ||
| 75 | &cpu2 { | |
| 76 | proc-supply = <&da9211_vcpu_reg>; | |
| 77 | sram-supply = <&mt6397_vsramca7_reg>; | |
| 78 | }; | |
| 79 | ||
| 80 | &cpu3 { | |
| 81 | proc-supply = <&da9211_vcpu_reg>; | |
| 82 | sram-supply = <&mt6397_vsramca7_reg>; | |
| 83 | }; |