Commit | Line | Data |
---|---|---|
96ae0b54 | 1 | * Gated Clock bindings for Marvell EBU SoCs |
f97d0d7a | 2 | |
e9646fe1 TP |
3 | Marvell Armada 370/375/380/385/XP, Dove and Kirkwood allow some |
4 | peripheral clocks to be gated to save some power. The clock consumer | |
5 | should specify the desired clock by having the clock ID in its | |
6 | "clocks" phandle cell. The clock ID is directly mapped to the | |
7 | corresponding clock gating control bit in HW to ease manual clock | |
96ae0b54 | 8 | lookup in datasheet. |
f97d0d7a | 9 | |
c4c34d60 GC |
10 | The following is a list of provided IDs for Armada 370: |
11 | ID Clock Peripheral | |
12 | ----------------------------------- | |
13 | 0 Audio AC97 Cntrl | |
14 | 1 pex0_en PCIe 0 Clock out | |
15 | 2 pex1_en PCIe 1 Clock out | |
16 | 3 ge1 Gigabit Ethernet 1 | |
17 | 4 ge0 Gigabit Ethernet 0 | |
18 | 5 pex0 PCIe Cntrl 0 | |
19 | 9 pex1 PCIe Cntrl 1 | |
20 | 15 sata0 SATA Host 0 | |
21 | 17 sdio SDHCI Host | |
22 | 25 tdm Time Division Mplx | |
23 | 28 ddr DDR Cntrl | |
24 | 30 sata1 SATA Host 0 | |
25 | ||
bac18c75 GC |
26 | The following is a list of provided IDs for Armada 375: |
27 | ID Clock Peripheral | |
28 | ----------------------------------- | |
29 | 2 mu Management Unit | |
30 | 3 pp Packet Processor | |
31 | 4 ptp PTP | |
32 | 5 pex0 PCIe 0 Clock out | |
33 | 6 pex1 PCIe 1 Clock out | |
34 | 8 audio Audio Cntrl | |
35 | 11 nd_clk Nand Flash Cntrl | |
36 | 14 sata0_link SATA 0 Link | |
37 | 15 sata0_core SATA 0 Core | |
38 | 16 usb3 USB3 Host | |
39 | 17 sdio SDHCI Host | |
40 | 18 usb USB Host | |
41 | 19 gop Gigabit Ethernet MAC | |
42 | 20 sata1_link SATA 1 Link | |
43 | 21 sata1_core SATA 1 Core | |
44 | 22 xor0 XOR DMA 0 | |
45 | 23 xor1 XOR DMA 0 | |
46 | 24 copro Coprocessor | |
47 | 25 tdm Time Division Mplx | |
48 | 28 crypto0_enc Cryptographic Unit Port 0 Encryption | |
49 | 29 crypto0_core Cryptographic Unit Port 0 Core | |
50 | 30 crypto1_enc Cryptographic Unit Port 1 Encryption | |
51 | 31 crypto1_core Cryptographic Unit Port 1 Core | |
52 | ||
e9646fe1 TP |
53 | The following is a list of provided IDs for Armada 380/385: |
54 | ID Clock Peripheral | |
55 | ----------------------------------- | |
56 | 0 audio Audio | |
57 | 2 ge2 Gigabit Ethernet 2 | |
58 | 3 ge1 Gigabit Ethernet 1 | |
59 | 4 ge0 Gigabit Ethernet 0 | |
60 | 5 pex1 PCIe 1 | |
61 | 6 pex2 PCIe 2 | |
62 | 7 pex3 PCIe 3 | |
63 | 8 pex0 PCIe 0 | |
64 | 9 usb3h0 USB3 Host 0 | |
65 | 10 usb3h1 USB3 Host 1 | |
66 | 11 usb3d USB3 Device | |
67 | 13 bm Buffer Management | |
68 | 14 crypto0z Cryptographic 0 Z | |
69 | 15 sata0 SATA 0 | |
70 | 16 crypto1z Cryptographic 1 Z | |
71 | 17 sdio SDIO | |
72 | 18 usb2 USB 2 | |
73 | 21 crypto1 Cryptographic 1 | |
74 | 22 xor0 XOR 0 | |
75 | 23 crypto0 Cryptographic 0 | |
76 | 25 tdm Time Division Multiplexing | |
77 | 28 xor1 XOR 1 | |
78 | 30 sata1 SATA 1 | |
bac18c75 | 79 | |
c4c34d60 GC |
80 | The following is a list of provided IDs for Armada XP: |
81 | ID Clock Peripheral | |
82 | ----------------------------------- | |
83 | 0 audio Audio Cntrl | |
84 | 1 ge3 Gigabit Ethernet 3 | |
85 | 2 ge2 Gigabit Ethernet 2 | |
86 | 3 ge1 Gigabit Ethernet 1 | |
87 | 4 ge0 Gigabit Ethernet 0 | |
88 | 5 pex0 PCIe Cntrl 0 | |
89 | 6 pex1 PCIe Cntrl 1 | |
90 | 7 pex2 PCIe Cntrl 2 | |
91 | 8 pex3 PCIe Cntrl 3 | |
92 | 13 bp | |
93 | 14 sata0lnk | |
94 | 15 sata0 SATA Host 0 | |
95 | 16 lcd LCD Cntrl | |
96 | 17 sdio SDHCI Host | |
97 | 18 usb0 USB Host 0 | |
98 | 19 usb1 USB Host 1 | |
99 | 20 usb2 USB Host 2 | |
100 | 22 xor0 XOR DMA 0 | |
101 | 23 crypto CESA engine | |
102 | 25 tdm Time Division Mplx | |
103 | 28 xor1 XOR DMA 1 | |
104 | 29 sata1lnk | |
105 | 30 sata1 SATA Host 0 | |
106 | ||
f97d0d7a SH |
107 | The following is a list of provided IDs for Dove: |
108 | ID Clock Peripheral | |
109 | ----------------------------------- | |
110 | 0 usb0 USB Host 0 | |
111 | 1 usb1 USB Host 1 | |
112 | 2 ge Gigabit Ethernet | |
113 | 3 sata SATA Host | |
114 | 4 pex0 PCIe Cntrl 0 | |
115 | 5 pex1 PCIe Cntrl 1 | |
116 | 8 sdio0 SDHCI Host 0 | |
117 | 9 sdio1 SDHCI Host 1 | |
118 | 10 nand NAND Cntrl | |
119 | 11 camera Camera Cntrl | |
120 | 12 i2s0 I2S Cntrl 0 | |
121 | 13 i2s1 I2S Cntrl 1 | |
122 | 15 crypto CESA engine | |
123 | 21 ac97 AC97 Cntrl | |
124 | 22 pdma Peripheral DMA | |
125 | 23 xor0 XOR DMA 0 | |
126 | 24 xor1 XOR DMA 1 | |
127 | 30 gephy Gigabit Ethernel PHY | |
128 | Note: gephy(30) is implemented as a parent clock of ge(2) | |
129 | ||
130 | The following is a list of provided IDs for Kirkwood: | |
131 | ID Clock Peripheral | |
132 | ----------------------------------- | |
133 | 0 ge0 Gigabit Ethernet 0 | |
134 | 2 pex0 PCIe Cntrl 0 | |
135 | 3 usb0 USB Host 0 | |
136 | 4 sdio SDIO Cntrl | |
137 | 5 tsu Transp. Stream Unit | |
138 | 6 dunit SDRAM Cntrl | |
139 | 7 runit Runit | |
140 | 8 xor0 XOR DMA 0 | |
141 | 9 audio I2S Cntrl 0 | |
142 | 14 sata0 SATA Host 0 | |
143 | 15 sata1 SATA Host 1 | |
144 | 16 xor1 XOR DMA 1 | |
145 | 17 crypto CESA engine | |
146 | 18 pex1 PCIe Cntrl 1 | |
7a87c8ab | 147 | 19 ge1 Gigabit Ethernet 1 |
f97d0d7a SH |
148 | 20 tdm Time Division Mplx |
149 | ||
150 | Required properties: | |
151 | - compatible : shall be one of the following: | |
96ae0b54 | 152 | "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating |
bac18c75 | 153 | "marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating |
e9646fe1 | 154 | "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating |
96ae0b54 | 155 | "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating |
f97d0d7a SH |
156 | "marvell,dove-gating-clock" - for Dove SoC clock gating |
157 | "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating | |
158 | - reg : shall be the register address of the Clock Gating Control register | |
159 | - #clock-cells : from common clock binding; shall be set to 1 | |
160 | ||
161 | Optional properties: | |
162 | - clocks : default parent clock phandle (e.g. tclk) | |
163 | ||
164 | Example: | |
165 | ||
166 | gate_clk: clock-gating-control@d0038 { | |
167 | compatible = "marvell,dove-gating-clock"; | |
168 | reg = <0xd0038 0x4>; | |
169 | /* default parent clock is tclk */ | |
170 | clocks = <&core_clk 0>; | |
171 | #clock-cells = <1>; | |
172 | }; | |
173 | ||
174 | sdio0: sdio@92000 { | |
175 | compatible = "marvell,dove-sdhci"; | |
176 | /* get clk gate bit 8 (sdio0) */ | |
177 | clocks = <&gate_clk 8>; | |
178 | }; |