Commit | Line | Data |
---|---|---|
abe844aa LP |
1 | * Renesas CPG DIV6 Clock |
2 | ||
3 | The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse | |
7a29f3f0 | 4 | Generator (CPG). Their clock input is divided by a configurable factor from 1 |
abe844aa LP |
5 | to 64. |
6 | ||
7 | Required Properties: | |
8 | ||
9 | - compatible: Must be one of the following | |
bfadcadf UH |
10 | - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks |
11 | - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks | |
abe844aa | 12 | - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks |
0e0d8b70 UH |
13 | - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks |
14 | - "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks | |
0c933f3a | 15 | - "renesas,r8a7794-div6-clock" for R8A7794 (R-Car E2) DIV6 clocks |
bfadcadf | 16 | - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks |
37062628 | 17 | and "renesas,cpg-div6-clock" as a fallback. |
abe844aa | 18 | - reg: Base address and length of the memory resource used by the DIV6 clock |
bfadcadf UH |
19 | - clocks: Reference to the parent clock(s); either one, four, or eight |
20 | clocks must be specified. For clocks with multiple parents, invalid | |
21 | settings must be specified as "<0>". | |
abe844aa LP |
22 | - #clock-cells: Must be 0 |
23 | - clock-output-names: The name of the clock as a free-form string | |
24 | ||
25 | ||
26 | Example | |
27 | ------- | |
28 | ||
bfadcadf UH |
29 | sdhi2_clk: sdhi2_clk@e615007c { |
30 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; | |
31 | reg = <0 0xe615007c 0 4>; | |
32 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
33 | <0>, <&extal2_clk>; | |
abe844aa | 34 | #clock-cells = <0>; |
bfadcadf | 35 | clock-output-names = "sdhi2ck"; |
abe844aa | 36 | }; |