Commit | Line | Data |
---|---|---|
f94859c2 LP |
1 | * Renesas CPG Module Stop (MSTP) Clocks |
2 | ||
3 | The CPG can gate SoC device clocks. The gates are organized in groups of up to | |
4 | 32 gates. | |
5 | ||
6 | This device tree binding describes a single 32 gate clocks group per node. | |
7 | Clocks are referenced by user nodes by the MSTP node phandle and the clock | |
8 | index in the group, from 0 to 31. | |
9 | ||
10 | Required Properties: | |
11 | ||
12 | - compatible: Must be one of the following | |
b557dead | 13 | - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks |
a2868160 | 14 | - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks |
b32c44b9 | 15 | - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks |
31a0b537 | 16 | - "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks |
5483bf69 | 17 | - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks |
f94859c2 | 18 | - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks |
b5405db9 | 19 | - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks |
ef71b1ea | 20 | - "renesas,r8a7792-mstp-clocks" for R8A7792 (R-Car V2H) MSTP gate clocks |
b5405db9 | 21 | - "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks |
5acb7bbb | 22 | - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks |
b32c44b9 | 23 | - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks |
17df1fb2 | 24 | and "renesas,cpg-mstp-clocks" as a fallback. |
f94859c2 LP |
25 | - reg: Base address and length of the I/O mapped registers used by the MSTP |
26 | clocks. The first register is the clock control register and is mandatory. | |
27 | The second register is the clock status register and is optional when not | |
28 | implemented in hardware. | |
29 | - clocks: Reference to the parent clocks, one per output clock. The parents | |
30 | must appear in the same order as the output clocks. | |
31 | - #clock-cells: Must be 1 | |
32 | - clock-output-names: The name of the clocks as free-form strings | |
29a77b8a | 33 | - clock-indices: Indices of the gate clocks into the group (0 to 31) |
f94859c2 | 34 | |
29a77b8a GU |
35 | The clocks, clock-output-names and clock-indices properties contain one entry |
36 | per gate clock. The MSTP groups are sparsely populated. Unimplemented gate | |
37 | clocks must not be declared. | |
f94859c2 LP |
38 | |
39 | ||
40 | Example | |
41 | ------- | |
42 | ||
43 | #include <dt-bindings/clock/r8a7790-clock.h> | |
44 | ||
45 | mstp3_clks: mstp3_clks@e615013c { | |
46 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
47 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; | |
48 | clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>, | |
49 | <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, | |
50 | <&mmc0_clk>; | |
51 | #clock-cells = <1>; | |
52 | clock-output-names = | |
53 | "tpu0", "mmcif1", "sdhi3", "sdhi2", | |
54 | "sdhi1", "sdhi0", "mmcif0"; | |
8e33f91a | 55 | clock-indices = < |
f94859c2 LP |
56 | R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 |
57 | R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 | |
58 | R8A7790_CLK_MMCIF0 | |
59 | >; | |
60 | }; |