Commit | Line | Data |
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10cdfe9f LP |
1 | * Renesas R-Car Gen2 Clock Pulse Generator (CPG) |
2 | ||
3 | The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs | |
4 | and several fixed ratio dividers. | |
63e05d93 GU |
5 | The CPG also provides a Clock Domain for SoC devices, in combination with the |
6 | CPG Module Stop (MSTP) Clocks. | |
10cdfe9f LP |
7 | |
8 | Required Properties: | |
9 | ||
10 | - compatible: Must be one of | |
11 | - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG | |
12 | - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG | |
caa96570 | 13 | - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG |
7466103c | 14 | - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG |
dd734a7e | 15 | and "renesas,rcar-gen2-cpg-clocks" as a fallback. |
10cdfe9f LP |
16 | |
17 | - reg: Base address and length of the memory resource used by the CPG | |
18 | ||
90cf0e2b SS |
19 | - clocks: References to the parent clocks: first to the EXTAL clock, second |
20 | to the USB_EXTAL clock | |
10cdfe9f LP |
21 | - #clock-cells: Must be 1 |
22 | - clock-output-names: The names of the clocks. Supported clocks are "main", | |
14842761 SS |
23 | "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and |
24 | "adsp" | |
63e05d93 | 25 | - #power-domain-cells: Must be 0 |
10cdfe9f | 26 | |
63e05d93 GU |
27 | SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed |
28 | through an MSTP clock should refer to the CPG device node in their | |
29 | "power-domains" property, as documented by the generic PM domain bindings in | |
30 | Documentation/devicetree/bindings/power/power_domain.txt. | |
10cdfe9f | 31 | |
63e05d93 GU |
32 | |
33 | Examples | |
34 | -------- | |
35 | ||
36 | - CPG device node: | |
10cdfe9f LP |
37 | |
38 | cpg_clocks: cpg_clocks@e6150000 { | |
39 | compatible = "renesas,r8a7790-cpg-clocks", | |
40 | "renesas,rcar-gen2-cpg-clocks"; | |
41 | reg = <0 0xe6150000 0 0x1000>; | |
90cf0e2b | 42 | clocks = <&extal_clk &usb_extal_clk>; |
10cdfe9f LP |
43 | #clock-cells = <1>; |
44 | clock-output-names = "main", "pll0, "pll1", "pll3", | |
90cf0e2b | 45 | "lb", "qspi", "sdh", "sd0", "sd1", "z", |
14842761 | 46 | "rcan", "adsp"; |
63e05d93 GU |
47 | #power-domain-cells = <0>; |
48 | }; | |
49 | ||
50 | ||
51 | - CPG/MSTP Clock Domain member device node: | |
52 | ||
53 | thermal@e61f0000 { | |
54 | compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal"; | |
55 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; | |
56 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; | |
57 | clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; | |
58 | power-domains = <&cpg_clocks>; | |
10cdfe9f | 59 | }; |