Commit | Line | Data |
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e874a669 EL |
1 | Device Tree Clock bindings for arch-sunxi |
2 | ||
3 | This binding uses the common clock binding[1]. | |
4 | ||
5 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | |
6 | ||
7 | Required properties: | |
8 | - compatible : shall be one of the following: | |
fd1b22f6 MR |
9 | "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator |
10 | "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4 | |
6a721db1 | 11 | "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31 |
515c1a4b | 12 | "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23 |
3b2bd70f | 13 | "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80 |
fd1b22f6 MR |
14 | "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock |
15 | "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock | |
92ef67c5 | 16 | "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31 |
3b2bd70f | 17 | "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80 |
fd1b22f6 MR |
18 | "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock |
19 | "allwinner,sun4i-a10-axi-clk" - for the AXI clock | |
515c1a4b | 20 | "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23 |
fd1b22f6 MR |
21 | "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates |
22 | "allwinner,sun4i-a10-ahb-clk" - for the AHB clock | |
9f243097 | 23 | "allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13 |
3b2bd70f | 24 | "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80 |
fd1b22f6 | 25 | "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10 |
4f985b4c | 26 | "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13 |
2371dd88 | 27 | "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s |
1fb2e4aa | 28 | "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20 |
5c89a8b6 | 29 | "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31 |
77d16e2c | 30 | "allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80 |
7954dfae | 31 | "allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31 |
ab6e23a4 | 32 | "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3 |
6a721db1 | 33 | "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 |
515c1a4b | 34 | "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23 |
0b0f0802 CYT |
35 | "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80 |
36 | "allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80 | |
37 | "allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80 | |
fd1b22f6 | 38 | "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock |
5c89a8b6 | 39 | "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31 |
57a1fbf2 | 40 | "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23 |
3b2bd70f | 41 | "allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80 |
fd1b22f6 | 42 | "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10 |
4f985b4c | 43 | "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13 |
2371dd88 | 44 | "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s |
5c89a8b6 | 45 | "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31 |
1fb2e4aa | 46 | "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20 |
6c1d66f0 | 47 | "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23 |
0b0f0802 | 48 | "allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80 |
fd1b22f6 | 49 | "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock |
3b2bd70f | 50 | "allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80 |
fd1b22f6 | 51 | "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10 |
4f985b4c | 52 | "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13 |
2371dd88 | 53 | "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s |
6a721db1 | 54 | "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31 |
1fb2e4aa | 55 | "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20 |
515c1a4b | 56 | "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23 |
0b0f0802 | 57 | "allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80 |
6a721db1 | 58 | "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 |
515c1a4b | 59 | "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23 |
ab6e23a4 | 60 | "allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3 |
bfcba2ed | 61 | "allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80 |
6d3a47c2 | 62 | "allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10 |
03e29bbf | 63 | "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13 |
6b0b8ccf | 64 | "allwinner,sun4i-a10-mmc-clk" - for the MMC clock |
61af4d8d | 65 | "allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80 |
7a6fca87 | 66 | "allwinner,sun9i-a80-mmc-config-clk" - for mmc gates + resets on A80 |
fd1b22f6 | 67 | "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks |
61af4d8d | 68 | "allwinner,sun9i-a80-mod0-clk" - for module 0 (storage) clocks on A80 |
9c8176bf | 69 | "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23 |
6f863417 | 70 | "allwinner,sun7i-a20-out-clk" - for the external output clocks |
e4c6d6c1 | 71 | "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31 |
5abdbf2f RB |
72 | "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20 |
73 | "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13 | |
6d1d14d5 | 74 | "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31 |
ec80749d | 75 | "allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23 |
7bec0200 | 76 | "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3 |
71f32f56 CYT |
77 | "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 |
78 | "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 | |
3cdd9f5c | 79 | "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock |
e874a669 EL |
80 | |
81 | Required properties for all clocks: | |
82 | - reg : shall be the control register address for the clock. | |
7551769a EL |
83 | - clocks : shall be the input parent clock(s) phandle for the clock. For |
84 | multiplexed clocks, the list order must match the hardware | |
85 | programming order. | |
13569a70 | 86 | - #clock-cells : from common clock binding; shall be set to 0 except for |
95e94c1f CYT |
87 | the following compatibles where it shall be set to 1: |
88 | "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk", | |
61af4d8d | 89 | "allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk", |
7a6fca87 CYT |
90 | "allwinner,*-usb-clk", "allwinner,*-mmc-clk", |
91 | "allwinner,*-mmc-config-clk" | |
373d4e6b CYT |
92 | - clock-output-names : shall be the corresponding names of the outputs. |
93 | If the clock module only has one output, the name shall be the | |
94 | module name. | |
e874a669 | 95 | |
5abdbf2f RB |
96 | And "allwinner,*-usb-clk" clocks also require: |
97 | - reset-cells : shall be set to 1 | |
98 | ||
3cdd9f5c CYT |
99 | The "allwinner,sun4i-a10-ve-clk" clock also requires: |
100 | - reset-cells : shall be set to 0 | |
101 | ||
7a6fca87 CYT |
102 | The "allwinner,sun9i-a80-mmc-config-clk" clock also requires: |
103 | - #reset-cells : shall be set to 1 | |
104 | - resets : shall be the reset control phandle for the mmc block. | |
105 | ||
e4c6d6c1 CYT |
106 | For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate |
107 | dummy clocks at 25 MHz and 125 MHz, respectively. See example. | |
108 | ||
4f985b4c MR |
109 | Clock consumers should specify the desired clocks they use with a |
110 | "clocks" phandle cell. Consumers that are using a gated clock should | |
fc42ef51 MR |
111 | provide an additional ID in their clock property. This ID is the |
112 | offset of the bit controlling this particular gate in the register. | |
95e94c1f CYT |
113 | For the other clocks with "#clock-cells" = 1, the additional ID shall |
114 | refer to the index of the output. | |
115 | ||
116 | For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output | |
117 | is the normal PLL6 output, or "pll6". The second output is rate doubled | |
118 | PLL6, or "pll6x2". | |
4f985b4c | 119 | |
61af4d8d | 120 | The "allwinner,*-mmc-clk" clocks have three different outputs: the |
6b0b8ccf MR |
121 | main clock, with the ID 0, and the output and sample clocks, with the |
122 | IDs 1 and 2, respectively. | |
123 | ||
7a6fca87 CYT |
124 | The "allwinner,sun9i-a80-mmc-config-clk" clock has one clock/reset output |
125 | per mmc controller. The number of outputs is determined by the size of | |
126 | the address block, which is related to the overall mmc block. | |
127 | ||
e874a669 EL |
128 | For example: |
129 | ||
373d4e6b | 130 | osc24M: clk@01c20050 { |
e874a669 | 131 | #clock-cells = <0>; |
fd1b22f6 | 132 | compatible = "allwinner,sun4i-a10-osc-clk"; |
e874a669 EL |
133 | reg = <0x01c20050 0x4>; |
134 | clocks = <&osc24M_fixed>; | |
373d4e6b | 135 | clock-output-names = "osc24M"; |
e874a669 EL |
136 | }; |
137 | ||
373d4e6b | 138 | pll1: clk@01c20000 { |
e874a669 | 139 | #clock-cells = <0>; |
fd1b22f6 | 140 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
e874a669 EL |
141 | reg = <0x01c20000 0x4>; |
142 | clocks = <&osc24M>; | |
373d4e6b CYT |
143 | clock-output-names = "pll1"; |
144 | }; | |
145 | ||
146 | pll5: clk@01c20020 { | |
147 | #clock-cells = <1>; | |
148 | compatible = "allwinner,sun4i-pll5-clk"; | |
149 | reg = <0x01c20020 0x4>; | |
150 | clocks = <&osc24M>; | |
151 | clock-output-names = "pll5_ddr", "pll5_other"; | |
e874a669 EL |
152 | }; |
153 | ||
95e94c1f CYT |
154 | pll6: clk@01c20028 { |
155 | #clock-cells = <1>; | |
156 | compatible = "allwinner,sun6i-a31-pll6-clk"; | |
157 | reg = <0x01c20028 0x4>; | |
158 | clocks = <&osc24M>; | |
159 | clock-output-names = "pll6", "pll6x2"; | |
160 | }; | |
161 | ||
e874a669 EL |
162 | cpu: cpu@01c20054 { |
163 | #clock-cells = <0>; | |
fd1b22f6 | 164 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
e874a669 EL |
165 | reg = <0x01c20054 0x4>; |
166 | clocks = <&osc32k>, <&osc24M>, <&pll1>; | |
373d4e6b CYT |
167 | clock-output-names = "cpu"; |
168 | }; | |
169 | ||
170 | mmc0_clk: clk@01c20088 { | |
6b0b8ccf MR |
171 | #clock-cells = <1>; |
172 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
373d4e6b CYT |
173 | reg = <0x01c20088 0x4>; |
174 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
6b0b8ccf | 175 | clock-output-names = "mmc0", "mmc0_output", "mmc0_sample"; |
e874a669 | 176 | }; |
e4c6d6c1 CYT |
177 | |
178 | mii_phy_tx_clk: clk@2 { | |
179 | #clock-cells = <0>; | |
180 | compatible = "fixed-clock"; | |
181 | clock-frequency = <25000000>; | |
182 | clock-output-names = "mii_phy_tx"; | |
183 | }; | |
184 | ||
185 | gmac_int_tx_clk: clk@3 { | |
186 | #clock-cells = <0>; | |
187 | compatible = "fixed-clock"; | |
188 | clock-frequency = <125000000>; | |
189 | clock-output-names = "gmac_int_tx"; | |
190 | }; | |
191 | ||
192 | gmac_clk: clk@01c20164 { | |
193 | #clock-cells = <0>; | |
194 | compatible = "allwinner,sun7i-a20-gmac-clk"; | |
195 | reg = <0x01c20164 0x4>; | |
196 | /* | |
197 | * The first clock must be fixed at 25MHz; | |
198 | * the second clock must be fixed at 125MHz | |
199 | */ | |
200 | clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; | |
201 | clock-output-names = "gmac"; | |
202 | }; | |
7a6fca87 CYT |
203 | |
204 | mmc_config_clk: clk@01c13000 { | |
205 | compatible = "allwinner,sun9i-a80-mmc-config-clk"; | |
206 | reg = <0x01c13000 0x10>; | |
207 | clocks = <&ahb0_gates 8>; | |
208 | clock-names = "ahb"; | |
209 | resets = <&ahb0_resets 8>; | |
210 | reset-names = "ahb"; | |
211 | #clock-cells = <1>; | |
212 | #reset-cells = <1>; | |
213 | clock-output-names = "mmc0_config", "mmc1_config", | |
214 | "mmc2_config", "mmc3_config"; | |
215 | }; |