[deliverable/linux.git] / Documentation / devicetree / bindings / clock / zx296702-clk.txt

Device Tree Clock bindings for ZTE zx296702

This binding uses the common clock binding[1].

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:
- compatible : shall be one of the following:
	"zte,zx296702-topcrm-clk":
		zx296702 top clock selection, divider and gating

	"zte,zx296702-lsp0crpm-clk" and
	"zte,zx296702-lsp1crpm-clk":
		zx296702 device level clock selection and gating

- reg: Address and length of the register set

The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296702-clock.h
for the full list of zx296702 clock IDs.


topclk: topcrm@0x09800000 {
        compatible = "zte,zx296702-topcrm-clk";
        reg = <0x09800000 0x1000>;
        #clock-cells = <1>;
};

uart0: serial@0x09405000 {
        compatible = "zte,zx296702-uart";
        reg = <0x09405000 0x1000>;
        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&lsp1clk ZX296702_UART0_PCLK>;
        status = "disabled";
};
Commit	Line	Data
d5553cb0 JN	1	Device Tree Clock bindings for ZTE zx296702
	2
	3	This binding uses the common clock binding[1].
	4
	5	[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
	6
	7	Required properties:
	8	- compatible : shall be one of the following:
	9	"zte,zx296702-topcrm-clk":
	10	zx296702 top clock selection, divider and gating
	11
	12	"zte,zx296702-lsp0crpm-clk" and
	13	"zte,zx296702-lsp1crpm-clk":
	14	zx296702 device level clock selection and gating
	15
	16	- reg: Address and length of the register set
	17
	18	The clock consumer should specify the desired clock by having the clock
	19	ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296702-clock.h
	20	for the full list of zx296702 clock IDs.
	21
	22
	23	topclk: topcrm@0x09800000 {
	24	compatible = "zte,zx296702-topcrm-clk";
	25	reg = <0x09800000 0x1000>;
	26	#clock-cells = <1>;
	27	};
	28
	29	uart0: serial@0x09405000 {
	30	compatible = "zte,zx296702-uart";
	31	reg = <0x09405000 0x1000>;
	32	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	33	clocks = <&lsp1clk ZX296702_UART0_PCLK>;
	34	status = "disabled";
	35	};