[deliverable/linux.git] / Documentation / devicetree / bindings / clock / zynq-7000.txt

Device Tree Clock bindings for the Zynq 7000 EPP

The Zynq EPP has several different clk providers, each with there own bindings.
The purpose of this document is to document their usage.

See clock_bindings.txt for more information on the generic clock bindings.
See Chapter 25 of Zynq TRM for more information about Zynq clocks.

== Clock Controller ==
The clock controller is a logical abstraction of Zynq's clock tree. It reads
required input clock frequencies from the devicetree and acts as clock provider
for all clock consumers of PS clocks.

Required properties:
 - #clock-cells : Must be 1
 - compatible : "xlnx,ps7-clkc"
 - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
		      (usually 33 MHz oscillators are used for Zynq platforms)
 - clock-output-names : List of strings used to name the clock outputs. Shall be
			a list of the outputs given below.

Optional properties:
 - clocks : as described in the clock bindings
 - clock-names : as described in the clock bindings
 - fclk-enable : Bit mask to enable FCLKs statically at boot time.
		 Bit [0..3] correspond to FCLK0..FCLK3. The corresponding
		 FCLK will only be enabled if it is actually running at
		 boot time.

Clock inputs:
The following strings are optional parameters to the 'clock-names' property in
order to provide an optional (E)MIO clock source.
 - swdt_ext_clk
 - gem0_emio_clk
 - gem1_emio_clk
 - mio_clk_XX		# with XX = 00..53
...

Clock outputs:
 0:  armpll
 1:  ddrpll
 2:  iopll
 3:  cpu_6or4x
 4:  cpu_3or2x
 5:  cpu_2x
 6:  cpu_1x
 7:  ddr2x
 8:  ddr3x
 9:  dci
 10: lqspi
 11: smc
 12: pcap
 13: gem0
 14: gem1
 15: fclk0
 16: fclk1
 17: fclk2
 18: fclk3
 19: can0
 20: can1
 21: sdio0
 22: sdio1
 23: uart0
 24: uart1
 25: spi0
 26: spi1
 27: dma
 28: usb0_aper
 29: usb1_aper
 30: gem0_aper
 31: gem1_aper
 32: sdio0_aper
 33: sdio1_aper
 34: spi0_aper
 35: spi1_aper
 36: can0_aper
 37: can1_aper
 38: i2c0_aper
 39: i2c1_aper
 40: uart0_aper
 41: uart1_aper
 42: gpio_aper
 43: lqspi_aper
 44: smc_aper
 45: swdt
 46: dbg_trc
 47: dbg_apb

Example:
	clkc: clkc {
		#clock-cells = <1>;
		compatible = "xlnx,ps7-clkc";
		ps-clk-frequency = <33333333>;
		clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
				"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
				"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
				"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
				"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
				"dma", "usb0_aper", "usb1_aper", "gem0_aper",
				"gem1_aper", "sdio0_aper", "sdio1_aper",
				"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
				"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
				"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
				"dbg_trc", "dbg_apb";
		# optional props
		clocks = <&clkc 16>, <&clk_foo>;
		clock-names = "gem1_emio_clk", "can_mio_clk_23";
	};
Commit	Line	Data
45aa2c27 JC	1	Device Tree Clock bindings for the Zynq 7000 EPP
	2
	3	The Zynq EPP has several different clk providers, each with there own bindings.
	4	The purpose of this document is to document their usage.
	5
	6	See clock_bindings.txt for more information on the generic clock bindings.
	7	See Chapter 25 of Zynq TRM for more information about Zynq clocks.
	8
0ee52b15 SB	9	== Clock Controller ==
	10	The clock controller is a logical abstraction of Zynq's clock tree. It reads
	11	required input clock frequencies from the devicetree and acts as clock provider
	12	for all clock consumers of PS clocks.
	13
	14	Required properties:
	15	- #clock-cells : Must be 1
	16	- compatible : "xlnx,ps7-clkc"
	17	- ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
	18	(usually 33 MHz oscillators are used for Zynq platforms)
	19	- clock-output-names : List of strings used to name the clock outputs. Shall be
	20	a list of the outputs given below.
	21
	22	Optional properties:
	23	- clocks : as described in the clock bindings
	24	- clock-names : as described in the clock bindings
ba52f8a9 SB	25	- fclk-enable : Bit mask to enable FCLKs statically at boot time.
	26	Bit [0..3] correspond to FCLK0..FCLK3. The corresponding
	27	FCLK will only be enabled if it is actually running at
	28	boot time.
0ee52b15 SB	29
	30	Clock inputs:
	31	The following strings are optional parameters to the 'clock-names' property in
	32	order to provide an optional (E)MIO clock source.
	33	- swdt_ext_clk
	34	- gem0_emio_clk
	35	- gem1_emio_clk
	36	- mio_clk_XX # with XX = 00..53
	37	...
	38
	39	Clock outputs:
	40	0: armpll
	41	1: ddrpll
	42	2: iopll
	43	3: cpu_6or4x
	44	4: cpu_3or2x
	45	5: cpu_2x
	46	6: cpu_1x
	47	7: ddr2x
	48	8: ddr3x
	49	9: dci
	50	10: lqspi
	51	11: smc
	52	12: pcap
	53	13: gem0
	54	14: gem1
	55	15: fclk0
	56	16: fclk1
	57	17: fclk2
	58	18: fclk3
	59	19: can0
	60	20: can1
	61	21: sdio0
	62	22: sdio1
	63	23: uart0
	64	24: uart1
	65	25: spi0
	66	26: spi1
	67	27: dma
	68	28: usb0_aper
	69	29: usb1_aper
	70	30: gem0_aper
	71	31: gem1_aper
	72	32: sdio0_aper
	73	33: sdio1_aper
	74	34: spi0_aper
	75	35: spi1_aper
	76	36: can0_aper
	77	37: can1_aper
	78	38: i2c0_aper
	79	39: i2c1_aper
	80	40: uart0_aper
	81	41: uart1_aper
	82	42: gpio_aper
	83	43: lqspi_aper
	84	44: smc_aper
	85	45: swdt
	86	46: dbg_trc
	87	47: dbg_apb
	88
	89	Example:
	90	clkc: clkc {
	91	#clock-cells = <1>;
	92	compatible = "xlnx,ps7-clkc";
93	ps-clk-frequency = <33333333>;
94	clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
95	"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
96	"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
97	"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
98	"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
99	"dma", "usb0_aper", "usb1_aper", "gem0_aper",
100	"gem1_aper", "sdio0_aper", "sdio1_aper",
101	"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
102	"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
103	"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
104	"dbg_trc", "dbg_apb";
105	# optional props
106	clocks = <&clkc 16>, <&clk_foo>;
107	clock-names = "gem1_emio_clk", "can_mio_clk_23";
108	};