[deliverable/linux.git] / Documentation / devicetree / bindings / crypto / fsl-sec4.txt

=====================================================================
SEC 4 Device Tree Binding
Copyright (C) 2008-2011 Freescale Semiconductor Inc.

 CONTENTS
   -Overview
   -SEC 4 Node
   -Job Ring Node
   -Run Time Integrity Check (RTIC) Node
   -Run Time Integrity Check (RTIC) Memory Node
   -Secure Non-Volatile Storage (SNVS) Node
   -Full Example

NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
Accelerator and Assurance Module (CAAM).

=====================================================================
Overview

DESCRIPTION

SEC 4 h/w can process requests from 2 types of sources.
1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
2. Job Rings (HW interface between cores & SEC 4 registers).

High Speed Data Path Configuration:

HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
such as the P4080.  The number of simultaneous dequeues the QI can make is
equal to the number of Descriptor Controller (DECO) engines in a particular
SEC version.  E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
dequeue from 5 subportals simultaneously.

Job Ring Data Path Configuration:

Each JR is located on a separate 4k page, they may (or may not) be made visible
in the memory partition devoted to a particular core.  The P4080 has 4 JRs, so
up to 4 JRs can be configured; and all 4 JRs process requests in parallel.

=====================================================================
SEC 4 Node

Description

    Node defines the base address of the SEC 4 block.
    This block specifies the address range of all global
    configuration registers for the SEC 4 block.  It
    also receives interrupts from the Run Time Integrity Check
    (RTIC) function within the SEC 4 block.

PROPERTIES

   - compatible
      Usage: required
      Value type: <string>
      Definition: Must include "fsl,sec-v4.0"

   - #address-cells
       Usage: required
       Value type: <u32>
       Definition: A standard property.  Defines the number of cells
           for representing physical addresses in child nodes.

   - #size-cells
       Usage: required
       Value type: <u32>
       Definition: A standard property.  Defines the number of cells
           for representing the size of physical addresses in
           child nodes.

   - reg
      Usage: required
      Value type: <prop-encoded-array>
      Definition: A standard property.  Specifies the physical
          address and length of the SEC4 configuration registers.
          registers

   - ranges
       Usage: required
       Value type: <prop-encoded-array>
       Definition: A standard property.  Specifies the physical address
           range of the SEC 4.0 register space (-SNVS not included).  A
           triplet that includes the child address, parent address, &
           length.

   - interrupts
      Usage: required
      Value type: <prop_encoded-array>
      Definition:  Specifies the interrupts generated by this
           device.  The value of the interrupts property
           consists of one interrupt specifier. The format
           of the specifier is defined by the binding document
           describing the node's interrupt parent.

   - interrupt-parent
      Usage: (required if interrupt property is defined)
      Value type: <phandle>
      Definition: A single <phandle> value that points
          to the interrupt parent to which the child domain
          is being mapped.

   Note: All other standard properties (see the ePAPR) are allowed
   but are optional.


EXAMPLE
	crypto@300000 {
		compatible = "fsl,sec-v4.0";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x300000 0x10000>;
		ranges = <0 0x300000 0x10000>;
		interrupt-parent = <&mpic>;
		interrupts = <92 2>;
	};

=====================================================================
Job Ring (JR) Node

    Child of the crypto node defines data processing interface to SEC 4
    across the peripheral bus for purposes of processing
    cryptographic descriptors. The specified address
    range can be made visible to one (or more) cores.
    The interrupt defined for this node is controlled within
    the address range of this node.

  - compatible
      Usage: required
      Value type: <string>
      Definition: Must include "fsl,sec-v4.0-job-ring"

  - reg
      Usage: required
      Value type: <prop-encoded-array>
      Definition: Specifies a two JR parameters:  an offset from
          the parent physical address and the length the JR registers.

   - fsl,liodn
       Usage: optional-but-recommended
       Value type: <prop-encoded-array>
       Definition:
           Specifies the LIODN to be used in conjunction with
           the ppid-to-liodn table that specifies the PPID to LIODN mapping.
           Needed if the PAMU is used.  Value is a 12 bit value
           where value is a LIODN ID for this JR. This property is
           normally set by boot firmware.

   - interrupts
      Usage: required
      Value type: <prop_encoded-array>
      Definition:  Specifies the interrupts generated by this
           device.  The value of the interrupts property
           consists of one interrupt specifier. The format
           of the specifier is defined by the binding document
           describing the node's interrupt parent.

   - interrupt-parent
      Usage: (required if interrupt property is defined)
      Value type: <phandle>
      Definition: A single <phandle> value that points
          to the interrupt parent to which the child domain
          is being mapped.

EXAMPLE
	jr@1000 {
		compatible = "fsl,sec-v4.0-job-ring";
		reg = <0x1000 0x1000>;
		fsl,liodn = <0x081>;
		interrupt-parent = <&mpic>;
		interrupts = <88 2>;
	};


=====================================================================
Run Time Integrity Check (RTIC) Node

  Child node of the crypto node.  Defines a register space that
  contains up to 5 sets of addresses and their lengths (sizes) that
  will be checked at run time.  After an initial hash result is
  calculated, these addresses are checked by HW to monitor any
  change.  If any memory is modified, a Security Violation is
  triggered (see SNVS definition).


  - compatible
      Usage: required
      Value type: <string>
      Definition: Must include "fsl,sec-v4.0-rtic".

   - #address-cells
       Usage: required
       Value type: <u32>
       Definition: A standard property.  Defines the number of cells
           for representing physical addresses in child nodes.  Must
           have a value of 1.

   - #size-cells
       Usage: required
       Value type: <u32>
       Definition: A standard property.  Defines the number of cells
           for representing the size of physical addresses in
           child nodes.  Must have a value of 1.

  - reg
      Usage: required
      Value type: <prop-encoded-array>
      Definition: A standard property.  Specifies a two parameters:
          an offset from the parent physical address and the length
          the SEC4 registers.

   - ranges
       Usage: required
       Value type: <prop-encoded-array>
       Definition: A standard property.  Specifies the physical address
           range of the SEC 4 register space (-SNVS not included).  A
           triplet that includes the child address, parent address, &
           length.

EXAMPLE
	rtic@6000 {
		compatible = "fsl,sec-v4.0-rtic";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x6000 0x100>;
		ranges = <0x0 0x6100 0xe00>;
	};

=====================================================================
Run Time Integrity Check (RTIC) Memory Node
  A child node that defines individual RTIC memory regions that are used to
  perform run-time integrity check of memory areas that should not modified.
  The node defines a register that contains the memory address &
  length (combined) and a second register that contains the hash result
  in big endian format.

  - compatible
      Usage: required
      Value type: <string>
      Definition: Must include "fsl,sec-v4.0-rtic-memory".

  - reg
      Usage: required
      Value type: <prop-encoded-array>
      Definition: A standard property.  Specifies two parameters:
          an offset from the parent physical address and the length:

          1. The location of the RTIC memory address & length registers.
          2. The location RTIC hash result.

  - fsl,rtic-region
       Usage: optional-but-recommended
       Value type: <prop-encoded-array>
       Definition:
           Specifies the HW address (36 bit address) for this region
           followed by the length of the HW partition to be checked;
           the address is represented as a 64 bit quantity followed
           by a 32 bit length.

   - fsl,liodn
       Usage: optional-but-recommended
       Value type: <prop-encoded-array>
       Definition:
           Specifies the LIODN to be used in conjunction with
           the ppid-to-liodn table that specifies the PPID to LIODN
           mapping.  Needed if the PAMU is used.  Value is a 12 bit value
           where value is a LIODN ID for this RTIC memory region. This
           property is normally set by boot firmware.

EXAMPLE
	rtic-a@0 {
		compatible = "fsl,sec-v4.0-rtic-memory";
		reg = <0x00 0x20 0x100 0x80>;
		fsl,liodn   = <0x03c>;
		fsl,rtic-region  = <0x12345678 0x12345678 0x12345678>;
	};

=====================================================================
Secure Non-Volatile Storage (SNVS) Node

    Node defines address range and the associated
    interrupt for the SNVS function.  This function
    monitors security state information & reports
    security violations.

  - compatible
      Usage: required
      Value type: <string>
      Definition: Must include "fsl,sec-v4.0-mon".

  - reg
      Usage: required
      Value type: <prop-encoded-array>
      Definition: A standard property.  Specifies the physical
          address and length of the SEC4 configuration
          registers.

   - interrupts
      Usage: required
      Value type: <prop_encoded-array>
      Definition:  Specifies the interrupts generated by this
           device.  The value of the interrupts property
           consists of one interrupt specifier. The format
           of the specifier is defined by the binding document
           describing the node's interrupt parent.

   - interrupt-parent
      Usage: (required if interrupt property is defined)
      Value type: <phandle>
      Definition: A single <phandle> value that points
          to the interrupt parent to which the child domain
          is being mapped.

EXAMPLE
	sec_mon@314000 {
		compatible = "fsl,sec-v4.0-mon";
		reg = <0x314000 0x1000>;
		interrupt-parent = <&mpic>;
		interrupts = <93 2>;
	};

=====================================================================
FULL EXAMPLE

	crypto: crypto@300000 {
		compatible = "fsl,sec-v4.0";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x300000 0x10000>;
		ranges = <0 0x300000 0x10000>;
		interrupt-parent = <&mpic>;
		interrupts = <92 2>;

		sec_jr0: jr@1000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x1000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <88 2>;
		};

		sec_jr1: jr@2000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <89 2>;
		};

		sec_jr2: jr@3000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x3000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <90 2>;
		};

		sec_jr3: jr@4000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x4000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <91 2>;
		};

		rtic@6000 {
			compatible = "fsl,sec-v4.0-rtic";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x6000 0x100>;
			ranges = <0x0 0x6100 0xe00>;

			rtic_a: rtic-a@0 {
				compatible = "fsl,sec-v4.0-rtic-memory";
				reg = <0x00 0x20 0x100 0x80>;
			};

			rtic_b: rtic-b@20 {
				compatible = "fsl,sec-v4.0-rtic-memory";
				reg = <0x20 0x20 0x200 0x80>;
			};

			rtic_c: rtic-c@40 {
				compatible = "fsl,sec-v4.0-rtic-memory";
				reg = <0x40 0x20 0x300 0x80>;
			};

			rtic_d: rtic-d@60 {
				compatible = "fsl,sec-v4.0-rtic-memory";
				reg = <0x60 0x20 0x500 0x80>;
			};
		};
	};

	sec_mon: sec_mon@314000 {
		compatible = "fsl,sec-v4.0-mon";
		reg = <0x314000 0x1000>;
		interrupt-parent = <&mpic>;
		interrupts = <93 2>;
	};

=====================================================================
Commit	Line	Data
8e8ec596 KP	1	=====================================================================
	2	SEC 4 Device Tree Binding
	3	Copyright (C) 2008-2011 Freescale Semiconductor Inc.
	4
	5	CONTENTS
	6	-Overview
	7	-SEC 4 Node
	8	-Job Ring Node
	9	-Run Time Integrity Check (RTIC) Node
	10	-Run Time Integrity Check (RTIC) Memory Node
	11	-Secure Non-Volatile Storage (SNVS) Node
	12	-Full Example
	13
	14	NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
	15	Accelerator and Assurance Module (CAAM).
	16
	17	=====================================================================
	18	Overview
	19
	20	DESCRIPTION
	21
	22	SEC 4 h/w can process requests from 2 types of sources.
	23	1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
	24	2. Job Rings (HW interface between cores & SEC 4 registers).
	25
	26	High Speed Data Path Configuration:
	27
	28	HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
	29	such as the P4080. The number of simultaneous dequeues the QI can make is
	30	equal to the number of Descriptor Controller (DECO) engines in a particular
	31	SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
	32	dequeue from 5 subportals simultaneously.
	33
	34	Job Ring Data Path Configuration:
	35
	36	Each JR is located on a separate 4k page, they may (or may not) be made visible
	37	in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
	38	up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
	39
	40	=====================================================================
7dfc2179	41	SEC 4 Node
8e8ec596 KP	42
	43	Description
	44
	45	Node defines the base address of the SEC 4 block.
	46	This block specifies the address range of all global
	47	configuration registers for the SEC 4 block. It
	48	also receives interrupts from the Run Time Integrity Check
	49	(RTIC) function within the SEC 4 block.
	50
	51	PROPERTIES
	52
	53	- compatible
	54	Usage: required
	55	Value type: <string>
7dfc2179	56	Definition: Must include "fsl,sec-v4.0"
8e8ec596 KP	57
	58	- #address-cells
	59	Usage: required
	60	Value type: <u32>
	61	Definition: A standard property. Defines the number of cells
	62	for representing physical addresses in child nodes.
	63
	64	- #size-cells
	65	Usage: required
	66	Value type: <u32>
	67	Definition: A standard property. Defines the number of cells
	68	for representing the size of physical addresses in
	69	child nodes.
	70
	71	- reg
	72	Usage: required
	73	Value type: <prop-encoded-array>
	74	Definition: A standard property. Specifies the physical
54e198d4	75	address and length of the SEC4 configuration registers.
8e8ec596 KP	76	registers
	77
	78	- ranges
	79	Usage: required
	80	Value type: <prop-encoded-array>
	81	Definition: A standard property. Specifies the physical address
	82	range of the SEC 4.0 register space (-SNVS not included). A
	83	triplet that includes the child address, parent address, &
	84	length.
	85
	86	- interrupts
	87	Usage: required
	88	Value type: <prop_encoded-array>
	89	Definition: Specifies the interrupts generated by this
	90	device. The value of the interrupts property
	91	consists of one interrupt specifier. The format
	92	of the specifier is defined by the binding document
	93	describing the node's interrupt parent.
	94
	95	- interrupt-parent
	96	Usage: (required if interrupt property is defined)
	97	Value type: <phandle>
	98	Definition: A single <phandle> value that points
	99	to the interrupt parent to which the child domain
	100	is being mapped.
	101
	102	Note: All other standard properties (see the ePAPR) are allowed
	103	but are optional.
	104
	105
	106	EXAMPLE
	107	crypto@300000 {
7dfc2179	108	compatible = "fsl,sec-v4.0";
8e8ec596 KP	109	#address-cells = <1>;
	110	#size-cells = <1>;
	111	reg = <0x300000 0x10000>;
	112	ranges = <0 0x300000 0x10000>;
	113	interrupt-parent = <&mpic>;
	114	interrupts = <92 2>;
	115	};
	116
	117	=====================================================================
7dfc2179	118	Job Ring (JR) Node
8e8ec596 KP	119
	120	Child of the crypto node defines data processing interface to SEC 4
	121	across the peripheral bus for purposes of processing
	122	cryptographic descriptors. The specified address
	123	range can be made visible to one (or more) cores.
	124	The interrupt defined for this node is controlled within
	125	the address range of this node.
	126
	127	- compatible
	128	Usage: required
	129	Value type: <string>
7dfc2179	130	Definition: Must include "fsl,sec-v4.0-job-ring"
8e8ec596 KP	131
	132	- reg
	133	Usage: required
	134	Value type: <prop-encoded-array>
	135	Definition: Specifies a two JR parameters: an offset from
	136	the parent physical address and the length the JR registers.
	137
	138	- fsl,liodn
	139	Usage: optional-but-recommended
	140	Value type: <prop-encoded-array>
	141	Definition:
	142	Specifies the LIODN to be used in conjunction with
	143	the ppid-to-liodn table that specifies the PPID to LIODN mapping.
	144	Needed if the PAMU is used. Value is a 12 bit value
	145	where value is a LIODN ID for this JR. This property is
	146	normally set by boot firmware.
	147
	148	- interrupts
	149	Usage: required
	150	Value type: <prop_encoded-array>
	151	Definition: Specifies the interrupts generated by this
	152	device. The value of the interrupts property
	153	consists of one interrupt specifier. The format
	154	of the specifier is defined by the binding document
	155	describing the node's interrupt parent.
	156
	157	- interrupt-parent
	158	Usage: (required if interrupt property is defined)
	159	Value type: <phandle>
	160	Definition: A single <phandle> value that points
	161	to the interrupt parent to which the child domain
	162	is being mapped.
	163
	164	EXAMPLE
	165	jr@1000 {
7dfc2179	166	compatible = "fsl,sec-v4.0-job-ring";
8e8ec596 KP	167	reg = <0x1000 0x1000>;
	168	fsl,liodn = <0x081>;
	169	interrupt-parent = <&mpic>;
	170	interrupts = <88 2>;
	171	};
	172
	173
	174	=====================================================================
7dfc2179	175	Run Time Integrity Check (RTIC) Node
8e8ec596 KP	176
	177	Child node of the crypto node. Defines a register space that
	178	contains up to 5 sets of addresses and their lengths (sizes) that
	179	will be checked at run time. After an initial hash result is
	180	calculated, these addresses are checked by HW to monitor any
	181	change. If any memory is modified, a Security Violation is
	182	triggered (see SNVS definition).
	183
	184
	185	- compatible
	186	Usage: required
	187	Value type: <string>
7dfc2179	188	Definition: Must include "fsl,sec-v4.0-rtic".
8e8ec596 KP	189
	190	- #address-cells
	191	Usage: required
	192	Value type: <u32>
	193	Definition: A standard property. Defines the number of cells
	194	for representing physical addresses in child nodes. Must
	195	have a value of 1.
	196
	197	- #size-cells
	198	Usage: required
	199	Value type: <u32>
	200	Definition: A standard property. Defines the number of cells
	201	for representing the size of physical addresses in
	202	child nodes. Must have a value of 1.
	203
	204	- reg
	205	Usage: required
	206	Value type: <prop-encoded-array>
	207	Definition: A standard property. Specifies a two parameters:
	208	an offset from the parent physical address and the length
	209	the SEC4 registers.
	210
	211	- ranges
	212	Usage: required
	213	Value type: <prop-encoded-array>
	214	Definition: A standard property. Specifies the physical address
	215	range of the SEC 4 register space (-SNVS not included). A
	216	triplet that includes the child address, parent address, &
	217	length.
	218
	219	EXAMPLE
	220	rtic@6000 {
7dfc2179	221	compatible = "fsl,sec-v4.0-rtic";
8e8ec596 KP	222	#address-cells = <1>;
	223	#size-cells = <1>;
	224	reg = <0x6000 0x100>;
	225	ranges = <0x0 0x6100 0xe00>;
	226	};
	227
	228	=====================================================================
7dfc2179	229	Run Time Integrity Check (RTIC) Memory Node
8e8ec596 KP	230	A child node that defines individual RTIC memory regions that are used to
	231	perform run-time integrity check of memory areas that should not modified.
	232	The node defines a register that contains the memory address &
	233	length (combined) and a second register that contains the hash result
	234	in big endian format.
	235
	236	- compatible
	237	Usage: required
	238	Value type: <string>
7dfc2179	239	Definition: Must include "fsl,sec-v4.0-rtic-memory".
8e8ec596 KP	240
	241	- reg
	242	Usage: required
	243	Value type: <prop-encoded-array>
	244	Definition: A standard property. Specifies two parameters:
	245	an offset from the parent physical address and the length:
	246
	247	1. The location of the RTIC memory address & length registers.
	248	2. The location RTIC hash result.
	249
	250	- fsl,rtic-region
	251	Usage: optional-but-recommended
	252	Value type: <prop-encoded-array>
	253	Definition:
	254	Specifies the HW address (36 bit address) for this region
	255	followed by the length of the HW partition to be checked;
	256	the address is represented as a 64 bit quantity followed
	257	by a 32 bit length.
	258
	259	- fsl,liodn
	260	Usage: optional-but-recommended
	261	Value type: <prop-encoded-array>
	262	Definition:
	263	Specifies the LIODN to be used in conjunction with
	264	the ppid-to-liodn table that specifies the PPID to LIODN
	265	mapping. Needed if the PAMU is used. Value is a 12 bit value
	266	where value is a LIODN ID for this RTIC memory region. This
	267	property is normally set by boot firmware.
	268
	269	EXAMPLE
	270	rtic-a@0 {
7dfc2179	271	compatible = "fsl,sec-v4.0-rtic-memory";
8e8ec596 KP	272	reg = <0x00 0x20 0x100 0x80>;
	273	fsl,liodn = <0x03c>;
	274	fsl,rtic-region = <0x12345678 0x12345678 0x12345678>;
	275	};
	276
	277	=====================================================================
7dfc2179	278	Secure Non-Volatile Storage (SNVS) Node
8e8ec596 KP	279
	280	Node defines address range and the associated
	281	interrupt for the SNVS function. This function
	282	monitors security state information & reports
	283	security violations.
	284
	285	- compatible
	286	Usage: required
	287	Value type: <string>
7dfc2179	288	Definition: Must include "fsl,sec-v4.0-mon".
8e8ec596 KP	289
	290	- reg
	291	Usage: required
	292	Value type: <prop-encoded-array>
	293	Definition: A standard property. Specifies the physical
	294	address and length of the SEC4 configuration
	295	registers.
	296
	297	- interrupts
	298	Usage: required
	299	Value type: <prop_encoded-array>
	300	Definition: Specifies the interrupts generated by this
	301	device. The value of the interrupts property
	302	consists of one interrupt specifier. The format
	303	of the specifier is defined by the binding document
	304	describing the node's interrupt parent.
	305
	306	- interrupt-parent
	307	Usage: (required if interrupt property is defined)
	308	Value type: <phandle>
	309	Definition: A single <phandle> value that points
	310	to the interrupt parent to which the child domain
	311	is being mapped.
	312
	313	EXAMPLE
	314	sec_mon@314000 {
7dfc2179	315	compatible = "fsl,sec-v4.0-mon";
8e8ec596 KP	316	reg = <0x314000 0x1000>;
	317	interrupt-parent = <&mpic>;
	318	interrupts = <93 2>;
	319	};
	320
	321	=====================================================================
	322	FULL EXAMPLE
	323
	324	crypto: crypto@300000 {
7dfc2179	325	compatible = "fsl,sec-v4.0";
8e8ec596 KP	326	#address-cells = <1>;
	327	#size-cells = <1>;
	328	reg = <0x300000 0x10000>;
	329	ranges = <0 0x300000 0x10000>;
	330	interrupt-parent = <&mpic>;
	331	interrupts = <92 2>;
	332
	333	sec_jr0: jr@1000 {
7dfc2179	334	compatible = "fsl,sec-v4.0-job-ring";
8e8ec596 KP	335	reg = <0x1000 0x1000>;
	336	interrupt-parent = <&mpic>;
	337	interrupts = <88 2>;
	338	};
	339
	340	sec_jr1: jr@2000 {
7dfc2179	341	compatible = "fsl,sec-v4.0-job-ring";
8e8ec596 KP	342	reg = <0x2000 0x1000>;
	343	interrupt-parent = <&mpic>;
	344	interrupts = <89 2>;
	345	};
	346
	347	sec_jr2: jr@3000 {
7dfc2179	348	compatible = "fsl,sec-v4.0-job-ring";
8e8ec596 KP	349	reg = <0x3000 0x1000>;
	350	interrupt-parent = <&mpic>;
	351	interrupts = <90 2>;
	352	};
	353
	354	sec_jr3: jr@4000 {
7dfc2179	355	compatible = "fsl,sec-v4.0-job-ring";
8e8ec596 KP	356	reg = <0x4000 0x1000>;
	357	interrupt-parent = <&mpic>;
	358	interrupts = <91 2>;
	359	};
	360
	361	rtic@6000 {
7dfc2179	362	compatible = "fsl,sec-v4.0-rtic";
8e8ec596 KP	363	#address-cells = <1>;
	364	#size-cells = <1>;
	365	reg = <0x6000 0x100>;
	366	ranges = <0x0 0x6100 0xe00>;
	367
	368	rtic_a: rtic-a@0 {
7dfc2179	369	compatible = "fsl,sec-v4.0-rtic-memory";
8e8ec596 KP	370	reg = <0x00 0x20 0x100 0x80>;
	371	};
	372
	373	rtic_b: rtic-b@20 {
7dfc2179	374	compatible = "fsl,sec-v4.0-rtic-memory";
8e8ec596 KP	375	reg = <0x20 0x20 0x200 0x80>;
	376	};
	377
	378	rtic_c: rtic-c@40 {
7dfc2179	379	compatible = "fsl,sec-v4.0-rtic-memory";
8e8ec596 KP	380	reg = <0x40 0x20 0x300 0x80>;
	381	};
	382
	383	rtic_d: rtic-d@60 {
7dfc2179	384	compatible = "fsl,sec-v4.0-rtic-memory";
8e8ec596 KP	385	reg = <0x60 0x20 0x500 0x80>;
	386	};
	387	};
	388	};
	389
	390	sec_mon: sec_mon@314000 {
7dfc2179	391	compatible = "fsl,sec-v4.0-mon";
8e8ec596 KP	392	reg = <0x314000 0x1000>;
	393	interrupt-parent = <&mpic>;
	394	interrupts = <93 2>;
	395	};
	396
	397	=====================================================================