[deliverable/linux.git] / Documentation / devicetree / bindings / crypto / fsl-sec4.txt

=====================================================================
SEC 4 Device Tree Binding
Copyright (C) 2008-2011 Freescale Semiconductor Inc.

 CONTENTS
   -Overview
   -SEC 4 Node
   -Job Ring Node
   -Run Time Integrity Check (RTIC) Node
   -Run Time Integrity Check (RTIC) Memory Node
   -Secure Non-Volatile Storage (SNVS) Node
   -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
   -Full Example

NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
Accelerator and Assurance Module (CAAM).

=====================================================================
Overview

DESCRIPTION

SEC 4 h/w can process requests from 2 types of sources.
1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
2. Job Rings (HW interface between cores & SEC 4 registers).

High Speed Data Path Configuration:

HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
such as the P4080.  The number of simultaneous dequeues the QI can make is
equal to the number of Descriptor Controller (DECO) engines in a particular
SEC version.  E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
dequeue from 5 subportals simultaneously.

Job Ring Data Path Configuration:

Each JR is located on a separate 4k page, they may (or may not) be made visible
in the memory partition devoted to a particular core.  The P4080 has 4 JRs, so
up to 4 JRs can be configured; and all 4 JRs process requests in parallel.

=====================================================================
SEC 4 Node

Description

    Node defines the base address of the SEC 4 block.
    This block specifies the address range of all global
    configuration registers for the SEC 4 block.  It
    also receives interrupts from the Run Time Integrity Check
    (RTIC) function within the SEC 4 block.

PROPERTIES

   - compatible
      Usage: required
      Value type: <string>
      Definition: Must include "fsl,sec-v4.0"

   - fsl,sec-era
      Usage: optional
      Value type: <u32>
      Definition: A standard property. Define the 'ERA' of the SEC
          device.

   - #address-cells
       Usage: required
       Value type: <u32>
       Definition: A standard property.  Defines the number of cells
           for representing physical addresses in child nodes.

   - #size-cells
       Usage: required
       Value type: <u32>
       Definition: A standard property.  Defines the number of cells
           for representing the size of physical addresses in
           child nodes.

   - reg
      Usage: required
      Value type: <prop-encoded-array>
      Definition: A standard property.  Specifies the physical
          address and length of the SEC4 configuration registers.
          registers

   - ranges
       Usage: required
       Value type: <prop-encoded-array>
       Definition: A standard property.  Specifies the physical address
           range of the SEC 4.0 register space (-SNVS not included).  A
           triplet that includes the child address, parent address, &
           length.

   - interrupts
      Usage: required
      Value type: <prop_encoded-array>
      Definition:  Specifies the interrupts generated by this
           device.  The value of the interrupts property
           consists of one interrupt specifier. The format
           of the specifier is defined by the binding document
           describing the node's interrupt parent.

   - interrupt-parent
      Usage: (required if interrupt property is defined)
      Value type: <phandle>
      Definition: A single <phandle> value that points
          to the interrupt parent to which the child domain
          is being mapped.

   Note: All other standard properties (see the ePAPR) are allowed
   but are optional.


EXAMPLE
	crypto@300000 {
		compatible = "fsl,sec-v4.0";
		fsl,sec-era = <2>;
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x300000 0x10000>;
		ranges = <0 0x300000 0x10000>;
		interrupt-parent = <&mpic>;
		interrupts = <92 2>;
	};

=====================================================================
Job Ring (JR) Node

    Child of the crypto node defines data processing interface to SEC 4
    across the peripheral bus for purposes of processing
    cryptographic descriptors. The specified address
    range can be made visible to one (or more) cores.
    The interrupt defined for this node is controlled within
    the address range of this node.

  - compatible
      Usage: required
      Value type: <string>
      Definition: Must include "fsl,sec-v4.0-job-ring"

  - reg
      Usage: required
      Value type: <prop-encoded-array>
      Definition: Specifies a two JR parameters:  an offset from
          the parent physical address and the length the JR registers.

   - fsl,liodn
       Usage: optional-but-recommended
       Value type: <prop-encoded-array>
       Definition:
           Specifies the LIODN to be used in conjunction with
           the ppid-to-liodn table that specifies the PPID to LIODN mapping.
           Needed if the PAMU is used.  Value is a 12 bit value
           where value is a LIODN ID for this JR. This property is
           normally set by boot firmware.

   - interrupts
      Usage: required
      Value type: <prop_encoded-array>
      Definition:  Specifies the interrupts generated by this
           device.  The value of the interrupts property
           consists of one interrupt specifier. The format
           of the specifier is defined by the binding document
           describing the node's interrupt parent.

   - interrupt-parent
      Usage: (required if interrupt property is defined)
      Value type: <phandle>
      Definition: A single <phandle> value that points
          to the interrupt parent to which the child domain
          is being mapped.

EXAMPLE
	jr@1000 {
		compatible = "fsl,sec-v4.0-job-ring";
		reg = <0x1000 0x1000>;
		fsl,liodn = <0x081>;
		interrupt-parent = <&mpic>;
		interrupts = <88 2>;
	};


=====================================================================
Run Time Integrity Check (RTIC) Node

  Child node of the crypto node.  Defines a register space that
  contains up to 5 sets of addresses and their lengths (sizes) that
  will be checked at run time.  After an initial hash result is
  calculated, these addresses are checked by HW to monitor any
  change.  If any memory is modified, a Security Violation is
  triggered (see SNVS definition).


  - compatible
      Usage: required
      Value type: <string>
      Definition: Must include "fsl,sec-v4.0-rtic".

   - #address-cells
       Usage: required
       Value type: <u32>
       Definition: A standard property.  Defines the number of cells
           for representing physical addresses in child nodes.  Must
           have a value of 1.

   - #size-cells
       Usage: required
       Value type: <u32>
       Definition: A standard property.  Defines the number of cells
           for representing the size of physical addresses in
           child nodes.  Must have a value of 1.

  - reg
      Usage: required
      Value type: <prop-encoded-array>
      Definition: A standard property.  Specifies a two parameters:
          an offset from the parent physical address and the length
          the SEC4 registers.

   - ranges
       Usage: required
       Value type: <prop-encoded-array>
       Definition: A standard property.  Specifies the physical address
           range of the SEC 4 register space (-SNVS not included).  A
           triplet that includes the child address, parent address, &
           length.

EXAMPLE
	rtic@6000 {
		compatible = "fsl,sec-v4.0-rtic";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x6000 0x100>;
		ranges = <0x0 0x6100 0xe00>;
	};

=====================================================================
Run Time Integrity Check (RTIC) Memory Node
  A child node that defines individual RTIC memory regions that are used to
  perform run-time integrity check of memory areas that should not modified.
  The node defines a register that contains the memory address &
  length (combined) and a second register that contains the hash result
  in big endian format.

  - compatible
      Usage: required
      Value type: <string>
      Definition: Must include "fsl,sec-v4.0-rtic-memory".

  - reg
      Usage: required
      Value type: <prop-encoded-array>
      Definition: A standard property.  Specifies two parameters:
          an offset from the parent physical address and the length:

          1. The location of the RTIC memory address & length registers.
          2. The location RTIC hash result.

  - fsl,rtic-region
       Usage: optional-but-recommended
       Value type: <prop-encoded-array>
       Definition:
           Specifies the HW address (36 bit address) for this region
           followed by the length of the HW partition to be checked;
           the address is represented as a 64 bit quantity followed
           by a 32 bit length.

   - fsl,liodn
       Usage: optional-but-recommended
       Value type: <prop-encoded-array>
       Definition:
           Specifies the LIODN to be used in conjunction with
           the ppid-to-liodn table that specifies the PPID to LIODN
           mapping.  Needed if the PAMU is used.  Value is a 12 bit value
           where value is a LIODN ID for this RTIC memory region. This
           property is normally set by boot firmware.

EXAMPLE
	rtic-a@0 {
		compatible = "fsl,sec-v4.0-rtic-memory";
		reg = <0x00 0x20 0x100 0x80>;
		fsl,liodn   = <0x03c>;
		fsl,rtic-region  = <0x12345678 0x12345678 0x12345678>;
	};

=====================================================================
Secure Non-Volatile Storage (SNVS) Node

    Node defines address range and the associated
    interrupt for the SNVS function.  This function
    monitors security state information & reports
    security violations. This also included rtc,
    system power off and ON/OFF key.

  - compatible
      Usage: required
      Value type: <string>
      Definition: Must include "fsl,sec-v4.0-mon" and "syscon".

  - reg
      Usage: required
      Value type: <prop-encoded-array>
      Definition: A standard property.  Specifies the physical
          address and length of the SEC4 configuration
          registers.

   - #address-cells
       Usage: required
       Value type: <u32>
       Definition: A standard property.  Defines the number of cells
           for representing physical addresses in child nodes.  Must
           have a value of 1.

   - #size-cells
       Usage: required
       Value type: <u32>
       Definition: A standard property.  Defines the number of cells
           for representing the size of physical addresses in
           child nodes.  Must have a value of 1.

   - ranges
       Usage: required
       Value type: <prop-encoded-array>
       Definition: A standard property.  Specifies the physical address
           range of the SNVS register space.  A triplet that includes
           the child address, parent address, & length.

   - interrupts
      Usage: optional
      Value type: <prop_encoded-array>
      Definition:  Specifies the interrupts generated by this
           device.  The value of the interrupts property
           consists of one interrupt specifier. The format
           of the specifier is defined by the binding document
           describing the node's interrupt parent.

   - interrupt-parent
      Usage: (required if interrupt property is defined)
      Value type: <phandle>
      Definition: A single <phandle> value that points
          to the interrupt parent to which the child domain
          is being mapped.

EXAMPLE
	sec_mon@314000 {
		compatible = "fsl,sec-v4.0-mon", "syscon";
		reg = <0x314000 0x1000>;
		ranges = <0 0x314000 0x1000>;
		interrupt-parent = <&mpic>;
		interrupts = <93 2>;
	};

=====================================================================
Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node

  A SNVS child node that defines SNVS LP RTC.

  - compatible
      Usage: required
      Value type: <string>
      Definition: Must include "fsl,sec-v4.0-mon-rtc-lp".

  - interrupts
      Usage: required
      Value type: <prop_encoded-array>
      Definition: Specifies the interrupts generated by this
	   device.  The value of the interrupts property
	   consists of one interrupt specifier. The format
	   of the specifier is defined by the binding document
	   describing the node's interrupt parent.

 - regmap
	Usage: required
	Value type: <phandle>
	Definition: this is phandle to the register map node.

 - offset
	Usage: option
	value type: <u32>
	Definition: LP register offset. default it is 0x34.

EXAMPLE
	sec_mon_rtc_lp@1 {
		compatible = "fsl,sec-v4.0-mon-rtc-lp";
		interrupts = <93 2>;
		regmap = <&snvs>;
		offset = <0x34>;
	};

=====================================================================
System ON/OFF key driver

  The snvs-pwrkey is designed to enable POWER key function which controlled
  by SNVS ONOFF, the driver can report the status of POWER key and wakeup
  system if pressed after system suspend.

  - compatible:
      Usage: required
      Value type: <string>
      Definition: Mush include "fsl,sec-v4.0-pwrkey".

  - interrupts:
      Usage: required
      Value type: <prop_encoded-array>
      Definition: The SNVS ON/OFF interrupt number to the CPU(s).

  - linux,keycode:
      Usage: option
      Value type: <int>
      Definition: Keycode to emit, KEY_POWER by default.

  - wakeup:
      Usage: option
      Value type: <boo>
      Definition: Button can wake-up the system.

 - regmap:
      Usage: required:
      Value type: <phandle>
      Definition: this is phandle to the register map node.

EXAMPLE:
	snvs-pwrkey@0x020cc000 {
		compatible = "fsl,sec-v4.0-pwrkey";
		regmap = <&snvs>;
		interrupts = <0 4 0x4>
	        linux,keycode = <116>; /* KEY_POWER */
		wakeup;
	};

=====================================================================
FULL EXAMPLE

	crypto: crypto@300000 {
		compatible = "fsl,sec-v4.0";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x300000 0x10000>;
		ranges = <0 0x300000 0x10000>;
		interrupt-parent = <&mpic>;
		interrupts = <92 2>;

		sec_jr0: jr@1000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x1000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <88 2>;
		};

		sec_jr1: jr@2000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <89 2>;
		};

		sec_jr2: jr@3000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x3000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <90 2>;
		};

		sec_jr3: jr@4000 {
			compatible = "fsl,sec-v4.0-job-ring";
			reg = <0x4000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <91 2>;
		};

		rtic@6000 {
			compatible = "fsl,sec-v4.0-rtic";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x6000 0x100>;
			ranges = <0x0 0x6100 0xe00>;

			rtic_a: rtic-a@0 {
				compatible = "fsl,sec-v4.0-rtic-memory";
				reg = <0x00 0x20 0x100 0x80>;
			};

			rtic_b: rtic-b@20 {
				compatible = "fsl,sec-v4.0-rtic-memory";
				reg = <0x20 0x20 0x200 0x80>;
			};

			rtic_c: rtic-c@40 {
				compatible = "fsl,sec-v4.0-rtic-memory";
				reg = <0x40 0x20 0x300 0x80>;
			};

			rtic_d: rtic-d@60 {
				compatible = "fsl,sec-v4.0-rtic-memory";
				reg = <0x60 0x20 0x500 0x80>;
			};
		};
	};

	sec_mon: sec_mon@314000 {
		compatible = "fsl,sec-v4.0-mon";
		reg = <0x314000 0x1000>;
		ranges = <0 0x314000 0x1000>;

		sec_mon_rtc_lp@34 {
			compatible = "fsl,sec-v4.0-mon-rtc-lp";
			regmap = <&sec_mon>;
			offset = <0x34>;
			interrupts = <93 2>;
		};

		snvs-pwrkey@0x020cc000 {
			compatible = "fsl,sec-v4.0-pwrkey";
			regmap = <&sec_mon>;
			interrupts = <0 4 0x4>;
			linux,keycode = <116>; /* KEY_POWER */
			wakeup;
		};
	};

=====================================================================
Commit	Line	Data
8e8ec596 KP	1	=====================================================================
	2	SEC 4 Device Tree Binding
	3	Copyright (C) 2008-2011 Freescale Semiconductor Inc.
	4
	5	CONTENTS
	6	-Overview
	7	-SEC 4 Node
	8	-Job Ring Node
	9	-Run Time Integrity Check (RTIC) Node
	10	-Run Time Integrity Check (RTIC) Memory Node
	11	-Secure Non-Volatile Storage (SNVS) Node
179a502f	12	-Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
8e8ec596 KP	13	-Full Example
	14
	15	NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
	16	Accelerator and Assurance Module (CAAM).
	17
	18	=====================================================================
	19	Overview
	20
	21	DESCRIPTION
	22
	23	SEC 4 h/w can process requests from 2 types of sources.
	24	1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
	25	2. Job Rings (HW interface between cores & SEC 4 registers).
	26
	27	High Speed Data Path Configuration:
	28
	29	HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
	30	such as the P4080. The number of simultaneous dequeues the QI can make is
	31	equal to the number of Descriptor Controller (DECO) engines in a particular
	32	SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
	33	dequeue from 5 subportals simultaneously.
	34
	35	Job Ring Data Path Configuration:
	36
	37	Each JR is located on a separate 4k page, they may (or may not) be made visible
	38	in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
	39	up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
	40
	41	=====================================================================
7dfc2179	42	SEC 4 Node
8e8ec596 KP	43
	44	Description
	45
	46	Node defines the base address of the SEC 4 block.
	47	This block specifies the address range of all global
	48	configuration registers for the SEC 4 block. It
	49	also receives interrupts from the Run Time Integrity Check
	50	(RTIC) function within the SEC 4 block.
	51
	52	PROPERTIES
	53
	54	- compatible
	55	Usage: required
	56	Value type: <string>
7eb9c5df VG	57	Definition: Must include "fsl,sec-v4.0"
	58
	59	- fsl,sec-era
	60	Usage: optional
	61	Value type: <u32>
	62	Definition: A standard property. Define the 'ERA' of the SEC
	63	device.
8e8ec596 KP	64
	65	- #address-cells
	66	Usage: required
	67	Value type: <u32>
	68	Definition: A standard property. Defines the number of cells
	69	for representing physical addresses in child nodes.
	70
	71	- #size-cells
	72	Usage: required
	73	Value type: <u32>
	74	Definition: A standard property. Defines the number of cells
	75	for representing the size of physical addresses in
	76	child nodes.
	77
	78	- reg
	79	Usage: required
	80	Value type: <prop-encoded-array>
	81	Definition: A standard property. Specifies the physical
54e198d4	82	address and length of the SEC4 configuration registers.
8e8ec596 KP	83	registers
	84
	85	- ranges
	86	Usage: required
	87	Value type: <prop-encoded-array>
	88	Definition: A standard property. Specifies the physical address
	89	range of the SEC 4.0 register space (-SNVS not included). A
	90	triplet that includes the child address, parent address, &
	91	length.
	92
	93	- interrupts
	94	Usage: required
	95	Value type: <prop_encoded-array>
	96	Definition: Specifies the interrupts generated by this
	97	device. The value of the interrupts property
	98	consists of one interrupt specifier. The format
	99	of the specifier is defined by the binding document
	100	describing the node's interrupt parent.
	101
	102	- interrupt-parent
	103	Usage: (required if interrupt property is defined)
	104	Value type: <phandle>
	105	Definition: A single <phandle> value that points
	106	to the interrupt parent to which the child domain
	107	is being mapped.
	108
	109	Note: All other standard properties (see the ePAPR) are allowed
	110	but are optional.
	111
	112
	113	EXAMPLE
	114	crypto@300000 {
7eb9c5df VG	115	compatible = "fsl,sec-v4.0";
7eb9c5df VG	116	fsl,sec-era = <2>;
8e8ec596 KP	117	#address-cells = <1>;
	118	#size-cells = <1>;
	119	reg = <0x300000 0x10000>;
	120	ranges = <0 0x300000 0x10000>;
	121	interrupt-parent = <&mpic>;
	122	interrupts = <92 2>;
	123	};
	124
	125	=====================================================================
7dfc2179	126	Job Ring (JR) Node
8e8ec596 KP	127
	128	Child of the crypto node defines data processing interface to SEC 4
	129	across the peripheral bus for purposes of processing
	130	cryptographic descriptors. The specified address
	131	range can be made visible to one (or more) cores.
	132	The interrupt defined for this node is controlled within
	133	the address range of this node.
	134
	135	- compatible
	136	Usage: required
	137	Value type: <string>
7dfc2179	138	Definition: Must include "fsl,sec-v4.0-job-ring"
8e8ec596 KP	139
	140	- reg
	141	Usage: required
	142	Value type: <prop-encoded-array>
	143	Definition: Specifies a two JR parameters: an offset from
	144	the parent physical address and the length the JR registers.
	145
	146	- fsl,liodn
	147	Usage: optional-but-recommended
	148	Value type: <prop-encoded-array>
	149	Definition:
	150	Specifies the LIODN to be used in conjunction with
	151	the ppid-to-liodn table that specifies the PPID to LIODN mapping.
	152	Needed if the PAMU is used. Value is a 12 bit value
	153	where value is a LIODN ID for this JR. This property is
	154	normally set by boot firmware.
	155
	156	- interrupts
	157	Usage: required
	158	Value type: <prop_encoded-array>
	159	Definition: Specifies the interrupts generated by this
	160	device. The value of the interrupts property
	161	consists of one interrupt specifier. The format
	162	of the specifier is defined by the binding document
	163	describing the node's interrupt parent.
	164
	165	- interrupt-parent
	166	Usage: (required if interrupt property is defined)
	167	Value type: <phandle>
	168	Definition: A single <phandle> value that points
	169	to the interrupt parent to which the child domain
	170	is being mapped.
	171
	172	EXAMPLE
	173	jr@1000 {
7dfc2179	174	compatible = "fsl,sec-v4.0-job-ring";
8e8ec596 KP	175	reg = <0x1000 0x1000>;
	176	fsl,liodn = <0x081>;
	177	interrupt-parent = <&mpic>;
	178	interrupts = <88 2>;
	179	};
	180
	181
	182	=====================================================================
7dfc2179	183	Run Time Integrity Check (RTIC) Node
8e8ec596 KP	184
	185	Child node of the crypto node. Defines a register space that
	186	contains up to 5 sets of addresses and their lengths (sizes) that
	187	will be checked at run time. After an initial hash result is
	188	calculated, these addresses are checked by HW to monitor any
	189	change. If any memory is modified, a Security Violation is
	190	triggered (see SNVS definition).
	191
	192
	193	- compatible
	194	Usage: required
	195	Value type: <string>
7dfc2179	196	Definition: Must include "fsl,sec-v4.0-rtic".
8e8ec596 KP	197
	198	- #address-cells
	199	Usage: required
	200	Value type: <u32>
	201	Definition: A standard property. Defines the number of cells
	202	for representing physical addresses in child nodes. Must
	203	have a value of 1.
	204
	205	- #size-cells
	206	Usage: required
	207	Value type: <u32>
	208	Definition: A standard property. Defines the number of cells
	209	for representing the size of physical addresses in
	210	child nodes. Must have a value of 1.
	211
	212	- reg
	213	Usage: required
	214	Value type: <prop-encoded-array>
	215	Definition: A standard property. Specifies a two parameters:
	216	an offset from the parent physical address and the length
	217	the SEC4 registers.
	218
	219	- ranges
	220	Usage: required
	221	Value type: <prop-encoded-array>
	222	Definition: A standard property. Specifies the physical address
	223	range of the SEC 4 register space (-SNVS not included). A
	224	triplet that includes the child address, parent address, &
	225	length.
	226
	227	EXAMPLE
	228	rtic@6000 {
7dfc2179	229	compatible = "fsl,sec-v4.0-rtic";
8e8ec596 KP	230	#address-cells = <1>;
	231	#size-cells = <1>;
	232	reg = <0x6000 0x100>;
	233	ranges = <0x0 0x6100 0xe00>;
	234	};
	235
	236	=====================================================================
7dfc2179	237	Run Time Integrity Check (RTIC) Memory Node
8e8ec596 KP	238	A child node that defines individual RTIC memory regions that are used to
	239	perform run-time integrity check of memory areas that should not modified.
	240	The node defines a register that contains the memory address &
	241	length (combined) and a second register that contains the hash result
	242	in big endian format.
	243
	244	- compatible
	245	Usage: required
	246	Value type: <string>
7dfc2179	247	Definition: Must include "fsl,sec-v4.0-rtic-memory".
8e8ec596 KP	248
	249	- reg
	250	Usage: required
	251	Value type: <prop-encoded-array>
	252	Definition: A standard property. Specifies two parameters:
	253	an offset from the parent physical address and the length:
	254
	255	1. The location of the RTIC memory address & length registers.
	256	2. The location RTIC hash result.
	257
	258	- fsl,rtic-region
	259	Usage: optional-but-recommended
	260	Value type: <prop-encoded-array>
	261	Definition:
	262	Specifies the HW address (36 bit address) for this region
	263	followed by the length of the HW partition to be checked;
	264	the address is represented as a 64 bit quantity followed
	265	by a 32 bit length.
	266
	267	- fsl,liodn
	268	Usage: optional-but-recommended
	269	Value type: <prop-encoded-array>
	270	Definition:
	271	Specifies the LIODN to be used in conjunction with
	272	the ppid-to-liodn table that specifies the PPID to LIODN
	273	mapping. Needed if the PAMU is used. Value is a 12 bit value
	274	where value is a LIODN ID for this RTIC memory region. This
	275	property is normally set by boot firmware.
	276
	277	EXAMPLE
	278	rtic-a@0 {
7dfc2179	279	compatible = "fsl,sec-v4.0-rtic-memory";
8e8ec596 KP	280	reg = <0x00 0x20 0x100 0x80>;
	281	fsl,liodn = <0x03c>;
	282	fsl,rtic-region = <0x12345678 0x12345678 0x12345678>;
	283	};
	284
	285	=====================================================================
7dfc2179	286	Secure Non-Volatile Storage (SNVS) Node
8e8ec596 KP	287
	288	Node defines address range and the associated
	289	interrupt for the SNVS function. This function
	290	monitors security state information & reports
4fcb7dfd FL	291	security violations. This also included rtc,
4fcb7dfd FL	292	system power off and ON/OFF key.
8e8ec596 KP	293
	294	- compatible
	295	Usage: required
	296	Value type: <string>
4fcb7dfd	297	Definition: Must include "fsl,sec-v4.0-mon" and "syscon".
8e8ec596 KP	298
	299	- reg
	300	Usage: required
	301	Value type: <prop-encoded-array>
	302	Definition: A standard property. Specifies the physical
	303	address and length of the SEC4 configuration
	304	registers.
	305
179a502f SG	306	- #address-cells
	307	Usage: required
	308	Value type: <u32>
	309	Definition: A standard property. Defines the number of cells
	310	for representing physical addresses in child nodes. Must
	311	have a value of 1.
	312
	313	- #size-cells
	314	Usage: required
	315	Value type: <u32>
	316	Definition: A standard property. Defines the number of cells
	317	for representing the size of physical addresses in
	318	child nodes. Must have a value of 1.
	319
	320	- ranges
	321	Usage: required
	322	Value type: <prop-encoded-array>
	323	Definition: A standard property. Specifies the physical address
	324	range of the SNVS register space. A triplet that includes
	325	the child address, parent address, & length.
	326
8e8ec596	327	- interrupts
4fcb7dfd	328	Usage: optional
8e8ec596 KP	329	Value type: <prop_encoded-array>
	330	Definition: Specifies the interrupts generated by this
	331	device. The value of the interrupts property
	332	consists of one interrupt specifier. The format
	333	of the specifier is defined by the binding document
	334	describing the node's interrupt parent.
	335
	336	- interrupt-parent
	337	Usage: (required if interrupt property is defined)
	338	Value type: <phandle>
	339	Definition: A single <phandle> value that points
	340	to the interrupt parent to which the child domain
	341	is being mapped.
	342
	343	EXAMPLE
	344	sec_mon@314000 {
4fcb7dfd	345	compatible = "fsl,sec-v4.0-mon", "syscon";
8e8ec596	346	reg = <0x314000 0x1000>;
179a502f	347	ranges = <0 0x314000 0x1000>;
8e8ec596 KP	348	interrupt-parent = <&mpic>;
	349	interrupts = <93 2>;
	350	};
	351
179a502f SG	352	=====================================================================
	353	Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
	354
	355	A SNVS child node that defines SNVS LP RTC.
	356
	357	- compatible
	358	Usage: required
	359	Value type: <string>
	360	Definition: Must include "fsl,sec-v4.0-mon-rtc-lp".
	361
4fcb7dfd	362	- interrupts
179a502f	363	Usage: required
4fcb7dfd FL	364	Value type: <prop_encoded-array>
	365	Definition: Specifies the interrupts generated by this
	366	device. The value of the interrupts property
	367	consists of one interrupt specifier. The format
	368	of the specifier is defined by the binding document
	369	describing the node's interrupt parent.
	370
	371	- regmap
	372	Usage: required
	373	Value type: <phandle>
	374	Definition: this is phandle to the register map node.
	375
	376	- offset
	377	Usage: option
	378	value type: <u32>
	379	Definition: LP register offset. default it is 0x34.
179a502f SG	380
179a502f SG	381	EXAMPLE
4fcb7dfd	382	sec_mon_rtc_lp@1 {
179a502f	383	compatible = "fsl,sec-v4.0-mon-rtc-lp";
4fcb7dfd FL	384	interrupts = <93 2>;
	385	regmap = <&snvs>;
	386	offset = <0x34>;
179a502f SG	387	};
179a502f SG	388
cc28791d FL	389	=====================================================================
	390	System ON/OFF key driver
	391
	392	The snvs-pwrkey is designed to enable POWER key function which controlled
	393	by SNVS ONOFF, the driver can report the status of POWER key and wakeup
	394	system if pressed after system suspend.
	395
	396	- compatible:
	397	Usage: required
	398	Value type: <string>
	399	Definition: Mush include "fsl,sec-v4.0-pwrkey".
	400
	401	- interrupts:
	402	Usage: required
	403	Value type: <prop_encoded-array>
	404	Definition: The SNVS ON/OFF interrupt number to the CPU(s).
	405
	406	- linux,keycode:
	407	Usage: option
	408	Value type: <int>
	409	Definition: Keycode to emit, KEY_POWER by default.
	410
	411	- wakeup:
	412	Usage: option
	413	Value type: <boo>
	414	Definition: Button can wake-up the system.
	415
	416	- regmap:
	417	Usage: required:
	418	Value type: <phandle>
	419	Definition: this is phandle to the register map node.
	420
	421	EXAMPLE:
	422	snvs-pwrkey@0x020cc000 {
	423	compatible = "fsl,sec-v4.0-pwrkey";
	424	regmap = <&snvs>;
	425	interrupts = <0 4 0x4>
	426	linux,keycode = <116>; /* KEY_POWER */
	427	wakeup;
	428	};
	429
8e8ec596 KP	430	=====================================================================
	431	FULL EXAMPLE
	432
	433	crypto: crypto@300000 {
7dfc2179	434	compatible = "fsl,sec-v4.0";
8e8ec596 KP	435	#address-cells = <1>;
	436	#size-cells = <1>;
	437	reg = <0x300000 0x10000>;
	438	ranges = <0 0x300000 0x10000>;
	439	interrupt-parent = <&mpic>;
	440	interrupts = <92 2>;
	441
	442	sec_jr0: jr@1000 {
7dfc2179	443	compatible = "fsl,sec-v4.0-job-ring";
8e8ec596 KP	444	reg = <0x1000 0x1000>;
	445	interrupt-parent = <&mpic>;
	446	interrupts = <88 2>;
	447	};
	448
	449	sec_jr1: jr@2000 {
7dfc2179	450	compatible = "fsl,sec-v4.0-job-ring";
8e8ec596 KP	451	reg = <0x2000 0x1000>;
	452	interrupt-parent = <&mpic>;
	453	interrupts = <89 2>;
	454	};
	455
	456	sec_jr2: jr@3000 {
7dfc2179	457	compatible = "fsl,sec-v4.0-job-ring";
8e8ec596 KP	458	reg = <0x3000 0x1000>;
	459	interrupt-parent = <&mpic>;
	460	interrupts = <90 2>;
	461	};
	462
	463	sec_jr3: jr@4000 {
7dfc2179	464	compatible = "fsl,sec-v4.0-job-ring";
8e8ec596 KP	465	reg = <0x4000 0x1000>;
	466	interrupt-parent = <&mpic>;
	467	interrupts = <91 2>;
	468	};
	469
	470	rtic@6000 {
7dfc2179	471	compatible = "fsl,sec-v4.0-rtic";
8e8ec596 KP	472	#address-cells = <1>;
	473	#size-cells = <1>;
	474	reg = <0x6000 0x100>;
	475	ranges = <0x0 0x6100 0xe00>;
	476
	477	rtic_a: rtic-a@0 {
7dfc2179	478	compatible = "fsl,sec-v4.0-rtic-memory";
8e8ec596 KP	479	reg = <0x00 0x20 0x100 0x80>;
	480	};
	481
	482	rtic_b: rtic-b@20 {
7dfc2179	483	compatible = "fsl,sec-v4.0-rtic-memory";
8e8ec596 KP	484	reg = <0x20 0x20 0x200 0x80>;
	485	};
	486
	487	rtic_c: rtic-c@40 {
7dfc2179	488	compatible = "fsl,sec-v4.0-rtic-memory";
8e8ec596 KP	489	reg = <0x40 0x20 0x300 0x80>;
	490	};
	491
	492	rtic_d: rtic-d@60 {
7dfc2179	493	compatible = "fsl,sec-v4.0-rtic-memory";
8e8ec596 KP	494	reg = <0x60 0x20 0x500 0x80>;
	495	};
	496	};
	497	};
	498
	499	sec_mon: sec_mon@314000 {
7dfc2179	500	compatible = "fsl,sec-v4.0-mon";
8e8ec596	501	reg = <0x314000 0x1000>;
179a502f	502	ranges = <0 0x314000 0x1000>;
179a502f SG	503
	504	sec_mon_rtc_lp@34 {
	505	compatible = "fsl,sec-v4.0-mon-rtc-lp";
4fcb7dfd FL	506	regmap = <&sec_mon>;
	507	offset = <0x34>;
	508	interrupts = <93 2>;
179a502f	509	};
cc28791d FL	510
	511	snvs-pwrkey@0x020cc000 {
	512	compatible = "fsl,sec-v4.0-pwrkey";
	513	regmap = <&sec_mon>;
	514	interrupts = <0 4 0x4>;
	515	linux,keycode = <116>; /* KEY_POWER */
	516	wakeup;
	517	};
8e8ec596 KP	518	};
	519
	520	=====================================================================