Commit | Line | Data |
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2400fc14 ID |
1 | Device-Tree bindings for Samsung Exynos Embedded DisplayPort Transmitter(eDP) |
2 | ||
3 | DisplayPort is industry standard to accommodate the growing board adoption | |
4 | of digital display technology within the PC and CE industries. | |
5 | It consolidates the internal and external connection methods to reduce device | |
6 | complexity and cost. It also supports necessary features for important cross | |
7 | industry applications and provides performance scalability to enable the next | |
8 | generation of displays that feature higher color depths, refresh rates, and | |
9 | display resolutions. | |
10 | ||
11 | eDP (embedded display port) device is compliant with Embedded DisplayPort | |
12 | standard as follows, | |
13 | - DisplayPort standard 1.1a for Exynos5250 and Exynos5260. | |
14 | - DisplayPort standard 1.3 for Exynos5422s and Exynos5800. | |
15 | ||
16 | eDP resides between FIMD and panel or FIMD and bridge such as LVDS. | |
17 | ||
825e90d0 AK |
18 | The Exynos display port interface should be configured based on |
19 | the type of panel connected to it. | |
20 | ||
21 | We use two nodes: | |
22 | -dp-controller node | |
23 | -dptx-phy node(defined inside dp-controller node) | |
24 | ||
25 | For the DP-PHY initialization, we use the dptx-phy node. | |
8114fabc JH |
26 | Required properties for dptx-phy: deprecated, use phys and phy-names |
27 | -reg: deprecated | |
825e90d0 | 28 | Base address of DP PHY register. |
8114fabc | 29 | -samsung,enable-mask: deprecated |
825e90d0 AK |
30 | The bit-mask used to enable/disable DP PHY. |
31 | ||
32 | For the Panel initialization, we read data from dp-controller node. | |
33 | Required properties for dp-controller: | |
34 | -compatible: | |
35 | should be "samsung,exynos5-dp". | |
36 | -reg: | |
37 | physical base address of the controller and length | |
38 | of memory mapped region. | |
39 | -interrupts: | |
40 | interrupt combiner values. | |
60e69858 JH |
41 | -clocks: |
42 | from common clock binding: handle to dp clock. | |
43 | -clock-names: | |
44 | from common clock binding: Shall be "dp". | |
825e90d0 AK |
45 | -interrupt-parent: |
46 | phandle to Interrupt combiner node. | |
8114fabc JH |
47 | -phys: |
48 | from general PHY binding: the phandle for the PHY device. | |
49 | -phy-names: | |
50 | from general PHY binding: Should be "dp". | |
825e90d0 AK |
51 | -samsung,color-space: |
52 | input video data format. | |
53 | COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2 | |
54 | -samsung,dynamic-range: | |
55 | dynamic range for input video data. | |
56 | VESA = 0, CEA = 1 | |
57 | -samsung,ycbcr-coeff: | |
58 | YCbCr co-efficients for input video. | |
59 | COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1 | |
60 | -samsung,color-depth: | |
61 | number of bits per colour component. | |
62 | COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3 | |
63 | -samsung,link-rate: | |
64 | link rate supported by the panel. | |
65 | LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A | |
66 | -samsung,lane-count: | |
67 | number of lanes supported by the panel. | |
68 | LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4 | |
1417f109 | 69 | - display-timings: timings for the connected panel as described by |
efdbd734 | 70 | Documentation/devicetree/bindings/display/display-timing.txt |
825e90d0 AK |
71 | |
72 | Optional properties for dp-controller: | |
73 | -interlaced: | |
74 | interlace scan mode. | |
75 | Progressive if defined, Interlaced if not defined | |
76 | -vsync-active-high: | |
77 | VSYNC polarity configuration. | |
78 | High if defined, Low if not defined | |
79 | -hsync-active-high: | |
80 | HSYNC polarity configuration. | |
81 | High if defined, Low if not defined | |
b8b52471 AB |
82 | -samsung,hpd-gpio: |
83 | Hotplug detect GPIO. | |
84 | Indicates which GPIO should be used for hotplug | |
85 | detection | |
2400fc14 ID |
86 | Video interfaces: |
87 | Device node can contain video interface port nodes according to [1]. | |
88 | The following are properties specific to those nodes: | |
89 | ||
90 | endpoint node connected to bridge or panel node: | |
91 | - remote-endpoint: specifies the endpoint in panel or bridge node. | |
92 | This node is required in all kinds of exynos dp | |
93 | to represent the connection between dp and bridge | |
94 | or dp and panel. | |
80185567 AK |
95 | |
96 | [1]: Documentation/devicetree/bindings/media/video-interfaces.txt | |
825e90d0 AK |
97 | |
98 | Example: | |
99 | ||
100 | SOC specific portion: | |
101 | dp-controller { | |
102 | compatible = "samsung,exynos5-dp"; | |
103 | reg = <0x145b0000 0x10000>; | |
104 | interrupts = <10 3>; | |
105 | interrupt-parent = <&combiner>; | |
60e69858 JH |
106 | clocks = <&clock 342>; |
107 | clock-names = "dp"; | |
825e90d0 | 108 | |
8114fabc JH |
109 | phys = <&dp_phy>; |
110 | phy-names = "dp"; | |
825e90d0 AK |
111 | }; |
112 | ||
113 | Board Specific portion: | |
114 | dp-controller { | |
115 | samsung,color-space = <0>; | |
116 | samsung,dynamic-range = <0>; | |
117 | samsung,ycbcr-coeff = <0>; | |
118 | samsung,color-depth = <1>; | |
119 | samsung,link-rate = <0x0a>; | |
120 | samsung,lane-count = <4>; | |
1417f109 SP |
121 | |
122 | display-timings { | |
123 | native-mode = <&lcd_timing>; | |
124 | lcd_timing: 1366x768 { | |
125 | clock-frequency = <70589280>; | |
126 | hactive = <1366>; | |
127 | vactive = <768>; | |
128 | hfront-porch = <40>; | |
129 | hback-porch = <40>; | |
130 | hsync-len = <32>; | |
131 | vback-porch = <10>; | |
132 | vfront-porch = <12>; | |
133 | vsync-len = <6>; | |
134 | }; | |
135 | }; | |
80185567 AK |
136 | |
137 | ports { | |
2400fc14 | 138 | port { |
80185567 | 139 | dp_out: endpoint { |
2400fc14 ID |
140 | remote-endpoint = <&dp_in>; |
141 | }; | |
142 | }; | |
143 | }; | |
144 | ||
145 | panel { | |
146 | ... | |
147 | port { | |
148 | dp_in: endpoint { | |
149 | remote-endpoint = <&dp_out>; | |
80185567 AK |
150 | }; |
151 | }; | |
152 | }; | |
825e90d0 | 153 | }; |