Commit | Line | Data |
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109eee2f JW |
1 | Device Tree bindings for Freescale DCU DRM Driver |
2 | ||
3 | Required properties: | |
4 | - compatible: Should be one of | |
5 | * "fsl,ls1021a-dcu". | |
6 | * "fsl,vf610-dcu". | |
7 | ||
8 | - reg: Address and length of the register set for dcu. | |
f93500f4 SA |
9 | - clocks: Handle to "dcu" and "pix" clock (in the order below) |
10 | This can be the same clock (e.g. LS1021a) | |
11 | See ../clocks/clock-bindings.txt for details. | |
12 | - clock-names: Should be "dcu" and "pix" | |
13 | See ../clocks/clock-bindings.txt for details. | |
109eee2f JW |
14 | - big-endian Boolean property, LS1021A DCU registers are big-endian. |
15 | - fsl,panel: The phandle to panel node. | |
16 | ||
fb127b79 SA |
17 | Optional properties: |
18 | - fsl,tcon: The phandle to the timing controller node. | |
19 | ||
109eee2f JW |
20 | Examples: |
21 | dcu: dcu@2ce0000 { | |
22 | compatible = "fsl,ls1021a-dcu"; | |
23 | reg = <0x0 0x2ce0000 0x0 0x10000>; | |
f93500f4 SA |
24 | clocks = <&platform_clk 0>, <&platform_clk 0>; |
25 | clock-names = "dcu", "pix"; | |
109eee2f JW |
26 | big-endian; |
27 | fsl,panel = <&panel>; | |
fb127b79 | 28 | fsl,tcon = <&tcon>; |
109eee2f | 29 | }; |