Commit | Line | Data |
---|---|---|
c760558c HL |
1 | Qualcomm Technologies Inc. adreno/snapdragon DSI output |
2 | ||
ec31abf6 | 3 | DSI Controller: |
c760558c HL |
4 | Required properties: |
5 | - compatible: | |
6 | * "qcom,mdss-dsi-ctrl" | |
ec31abf6 | 7 | - reg: Physical base address and length of the registers of controller |
c760558c HL |
8 | - reg-names: The names of register regions. The following regions are required: |
9 | * "dsi_ctrl" | |
c760558c HL |
10 | - qcom,dsi-host-index: The ID of DSI controller hardware instance. This should |
11 | be 0 or 1, since we have 2 DSI controllers at most for now. | |
12 | - interrupts: The interrupt signal from the DSI block. | |
13 | - power-domains: Should be <&mmcc MDSS_GDSC>. | |
a3c463e0 | 14 | - clocks: Phandles to device clocks. |
c760558c | 15 | - clock-names: the following clocks are required: |
60834ca1 AT |
16 | * "mdp_core_clk" |
17 | * "iface_clk" | |
c760558c | 18 | * "bus_clk" |
c760558c | 19 | * "core_mmss_clk" |
60834ca1 | 20 | * "byte_clk" |
c760558c | 21 | * "pixel_clk" |
60834ca1 | 22 | * "core_clk" |
6dc13410 AT |
23 | For DSIv2, we need an additional clock: |
24 | * "src_clk" | |
9097209d AT |
25 | - assigned-clocks: Parents of "byte_clk" and "pixel_clk" for the given platform. |
26 | - assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided | |
a3c463e0 | 27 | by a DSI PHY block. See [1] for details on clock bindings. |
c760558c HL |
28 | - vdd-supply: phandle to vdd regulator device node |
29 | - vddio-supply: phandle to vdd-io regulator device node | |
30 | - vdda-supply: phandle to vdda regulator device node | |
8042b778 AT |
31 | - phys: phandle to DSI PHY device node |
32 | - phy-names: the name of the corresponding PHY device | |
6dc13410 | 33 | - syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2) |
8042b778 | 34 | - ports: Contains 2 DSI controller ports as child nodes. Each port contains |
a3c463e0 | 35 | an endpoint subnode as defined in [2] and [3]. |
c760558c HL |
36 | |
37 | Optional properties: | |
38 | - panel@0: Node of panel connected to this DSI controller. | |
a3c463e0 | 39 | See files in [4] for each supported panel. |
678565c3 | 40 | - qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is |
c760558c | 41 | driving a panel which needs 2 DSI links. |
678565c3 | 42 | - qcom,master-dsi: Boolean value indicating if the DSI controller is driving |
c760558c | 43 | the master link of the 2-DSI panel. |
678565c3 | 44 | - qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is |
c760558c HL |
45 | driving a 2-DSI panel whose 2 links need receive command simultaneously. |
46 | - interrupt-parent: phandle to the MDP block if the interrupt signal is routed | |
47 | through MDP block | |
ab8909b0 HL |
48 | - pinctrl-names: the pin control state names; should contain "default" |
49 | - pinctrl-0: the default pinctrl state (active) | |
50 | - pinctrl-n: the "sleep" pinctrl state | |
8042b778 AT |
51 | - ports: contains DSI controller input and output ports as children, each |
52 | containing one endpoint subnode. | |
26f7d1f4 AT |
53 | |
54 | DSI Endpoint properties: | |
8042b778 | 55 | - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's |
a3c463e0 AT |
56 | input endpoint. For port@1, set to the MDP interface output. See [2] for |
57 | device graph info. | |
8042b778 | 58 | |
cb9b08e9 AT |
59 | - data-lanes: this describes how the physical DSI data lanes are mapped |
60 | to the logical lanes on the given platform. The value contained in | |
61 | index n describes what physical lane is mapped to the logical lane n | |
62 | (DATAn, where n lies between 0 and 3). The clock lane position is fixed | |
a3c463e0 AT |
63 | and can't be changed. Hence, they aren't a part of the DT bindings. See |
64 | [3] for more info on the data-lanes property. | |
26f7d1f4 AT |
65 | |
66 | For example: | |
67 | ||
cb9b08e9 | 68 | data-lanes = <3 0 1 2>; |
26f7d1f4 | 69 | |
cb9b08e9 AT |
70 | The above mapping describes that the logical data lane DATA0 is mapped to |
71 | the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2 | |
72 | to phys DATA1 and logic DATA3 to phys DATA2. | |
26f7d1f4 AT |
73 | |
74 | There are only a limited number of physical to logical mappings possible: | |
cb9b08e9 AT |
75 | <0 1 2 3> |
76 | <1 2 3 0> | |
77 | <2 3 0 1> | |
78 | <3 0 1 2> | |
79 | <0 3 2 1> | |
80 | <1 0 3 2> | |
81 | <2 1 0 3> | |
82 | <3 2 1 0> | |
c760558c | 83 | |
ec31abf6 HL |
84 | DSI PHY: |
85 | Required properties: | |
86 | - compatible: Could be the following | |
87 | * "qcom,dsi-phy-28nm-hpm" | |
88 | * "qcom,dsi-phy-28nm-lp" | |
dcefc117 | 89 | * "qcom,dsi-phy-20nm" |
6dc13410 | 90 | * "qcom,dsi-phy-28nm-8960" |
ec31abf6 HL |
91 | - reg: Physical base address and length of the registers of PLL, PHY and PHY |
92 | regulator | |
93 | - reg-names: The names of register regions. The following regions are required: | |
94 | * "dsi_pll" | |
95 | * "dsi_phy" | |
96 | * "dsi_phy_regulator" | |
9097209d AT |
97 | - clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating |
98 | 2 clocks: A byte clock (index 0), and a pixel clock (index 1). | |
ec31abf6 HL |
99 | - qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should |
100 | be 0 or 1, since we have 2 DSI PHYs at most for now. | |
101 | - power-domains: Should be <&mmcc MDSS_GDSC>. | |
a3c463e0 | 102 | - clocks: Phandles to device clocks. See [1] for details on clock bindings. |
ec31abf6 HL |
103 | - clock-names: the following clocks are required: |
104 | * "iface_clk" | |
105 | - vddio-supply: phandle to vdd-io regulator device node | |
106 | ||
dcefc117 HL |
107 | Optional properties: |
108 | - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY | |
109 | regulator is wanted. | |
110 | ||
a3c463e0 AT |
111 | [1] Documentation/devicetree/bindings/clocks/clock-bindings.txt |
112 | [2] Documentation/devicetree/bindings/graph.txt | |
113 | [3] Documentation/devicetree/bindings/media/video-interfaces.txt | |
114 | [4] Documentation/devicetree/bindings/display/panel/ | |
115 | ||
c760558c | 116 | Example: |
a3c463e0 | 117 | dsi0: dsi@fd922800 { |
c760558c HL |
118 | compatible = "qcom,mdss-dsi-ctrl"; |
119 | qcom,dsi-host-index = <0>; | |
a3c463e0 | 120 | interrupt-parent = <&mdp>; |
c760558c | 121 | interrupts = <4 0>; |
ec31abf6 HL |
122 | reg-names = "dsi_ctrl"; |
123 | reg = <0xfd922800 0x200>; | |
c760558c HL |
124 | power-domains = <&mmcc MDSS_GDSC>; |
125 | clock-names = | |
126 | "bus_clk", | |
127 | "byte_clk", | |
128 | "core_clk", | |
129 | "core_mmss_clk", | |
130 | "iface_clk", | |
131 | "mdp_core_clk", | |
132 | "pixel_clk"; | |
133 | clocks = | |
134 | <&mmcc MDSS_AXI_CLK>, | |
135 | <&mmcc MDSS_BYTE0_CLK>, | |
136 | <&mmcc MDSS_ESC0_CLK>, | |
137 | <&mmcc MMSS_MISC_AHB_CLK>, | |
138 | <&mmcc MDSS_AHB_CLK>, | |
139 | <&mmcc MDSS_MDP_CLK>, | |
140 | <&mmcc MDSS_PCLK0_CLK>; | |
9097209d AT |
141 | |
142 | assigned-clocks = | |
143 | <&mmcc BYTE0_CLK_SRC>, | |
144 | <&mmcc PCLK0_CLK_SRC>; | |
145 | assigned-clock-parents = | |
a3c463e0 AT |
146 | <&dsi_phy0 0>, |
147 | <&dsi_phy0 1>; | |
9097209d | 148 | |
c760558c HL |
149 | vdda-supply = <&pma8084_l2>; |
150 | vdd-supply = <&pma8084_l22>; | |
151 | vddio-supply = <&pma8084_l12>; | |
152 | ||
a3c463e0 | 153 | phys = <&dsi_phy0>; |
8042b778 | 154 | phy-names ="dsi-phy"; |
ec31abf6 | 155 | |
678565c3 HL |
156 | qcom,dual-dsi-mode; |
157 | qcom,master-dsi; | |
158 | qcom,sync-dual-dsi; | |
c760558c | 159 | |
ab8909b0 | 160 | pinctrl-names = "default", "sleep"; |
a3c463e0 AT |
161 | pinctrl-0 = <&dsi_active>; |
162 | pinctrl-1 = <&dsi_suspend>; | |
ab8909b0 | 163 | |
8042b778 AT |
164 | ports { |
165 | #address-cells = <1>; | |
166 | #size-cells = <0>; | |
167 | ||
168 | port@0 { | |
169 | reg = <0>; | |
170 | dsi0_in: endpoint { | |
171 | remote-endpoint = <&mdp_intf1_out>; | |
172 | }; | |
173 | }; | |
174 | ||
175 | port@1 { | |
176 | reg = <1>; | |
177 | dsi0_out: endpoint { | |
178 | remote-endpoint = <&panel_in>; | |
179 | data-lanes = <0 1 2 3>; | |
180 | }; | |
181 | }; | |
182 | }; | |
183 | ||
c760558c HL |
184 | panel: panel@0 { |
185 | compatible = "sharp,lq101r1sx01"; | |
186 | reg = <0>; | |
187 | link2 = <&secondary>; | |
188 | ||
189 | power-supply = <...>; | |
190 | backlight = <...>; | |
f7009d26 AT |
191 | |
192 | port { | |
193 | panel_in: endpoint { | |
194 | remote-endpoint = <&dsi0_out>; | |
195 | }; | |
196 | }; | |
197 | }; | |
c760558c | 198 | }; |
ec31abf6 | 199 | |
a3c463e0 | 200 | dsi_phy0: dsi-phy@fd922a00 { |
ec31abf6 HL |
201 | compatible = "qcom,dsi-phy-28nm-hpm"; |
202 | qcom,dsi-phy-index = <0>; | |
203 | reg-names = | |
204 | "dsi_pll", | |
205 | "dsi_phy", | |
206 | "dsi_phy_regulator"; | |
207 | reg = <0xfd922a00 0xd4>, | |
208 | <0xfd922b00 0x2b0>, | |
209 | <0xfd922d80 0x7b>; | |
210 | clock-names = "iface_clk"; | |
211 | clocks = <&mmcc MDSS_AHB_CLK>; | |
9097209d | 212 | #clock-cells = <1>; |
ec31abf6 | 213 | vddio-supply = <&pma8084_l12>; |
dcefc117 HL |
214 | |
215 | qcom,dsi-phy-regulator-ldo-mode; | |
ec31abf6 | 216 | }; |