[deliverable/linux.git] / Documentation / devicetree / bindings / display / tegra / nvidia,tegra20-host1x.txt

NVIDIA Tegra host1x

Required properties:
- compatible: "nvidia,tegra<chip>-host1x"
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller.
- #address-cells: The number of cells used to represent physical base addresses
  in the host1x address space. Should be 1.
- #size-cells: The number of cells used to represent the size of an address
  range in the host1x address space. Should be 1.
- ranges: The mapping of the host1x address space to the CPU address space.
- clocks: Must contain one entry, for the module clock.
  See ../clocks/clock-bindings.txt for details.
- resets: Must contain an entry for each entry in reset-names.
  See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
  - host1x

The host1x top-level node defines a number of children, each representing one
of the following host1x client modules:

- mpe: video encoder

  Required properties:
  - compatible: "nvidia,tegra<chip>-mpe"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain one entry, for the module clock.
    See ../clocks/clock-bindings.txt for details.
  - resets: Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.
  - reset-names: Must include the following entries:
    - mpe

- vi: video input

  Required properties:
  - compatible: "nvidia,tegra<chip>-vi"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain one entry, for the module clock.
    See ../clocks/clock-bindings.txt for details.
  - resets: Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.
  - reset-names: Must include the following entries:
    - vi

- epp: encoder pre-processor

  Required properties:
  - compatible: "nvidia,tegra<chip>-epp"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain one entry, for the module clock.
    See ../clocks/clock-bindings.txt for details.
  - resets: Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.
  - reset-names: Must include the following entries:
    - epp

- isp: image signal processor

  Required properties:
  - compatible: "nvidia,tegra<chip>-isp"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain one entry, for the module clock.
    See ../clocks/clock-bindings.txt for details.
  - resets: Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.
  - reset-names: Must include the following entries:
    - isp

- gr2d: 2D graphics engine

  Required properties:
  - compatible: "nvidia,tegra<chip>-gr2d"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain one entry, for the module clock.
    See ../clocks/clock-bindings.txt for details.
  - resets: Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.
  - reset-names: Must include the following entries:
    - 2d

- gr3d: 3D graphics engine

  Required properties:
  - compatible: "nvidia,tegra<chip>-gr3d"
  - reg: Physical base address and length of the controller's registers.
  - clocks: Must contain an entry for each entry in clock-names.
    See ../clocks/clock-bindings.txt for details.
  - clock-names: Must include the following entries:
    (This property may be omitted if the only clock in the list is "3d")
    - 3d
      This MUST be the first entry.
    - 3d2 (Only required on SoCs with two 3D clocks)
  - resets: Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.
  - reset-names: Must include the following entries:
    - 3d
    - 3d2 (Only required on SoCs with two 3D clocks)

- dc: display controller

  Required properties:
  - compatible: "nvidia,tegra<chip>-dc"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain an entry for each entry in clock-names.
    See ../clocks/clock-bindings.txt for details.
  - clock-names: Must include the following entries:
    - dc
      This MUST be the first entry.
    - parent
  - resets: Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.
  - reset-names: Must include the following entries:
    - dc
  - nvidia,head: The number of the display controller head. This is used to
    setup the various types of output to receive video data from the given
    head.

  Each display controller node has a child node, named "rgb", that represents
  the RGB output associated with the controller. It can take the following
  optional properties:
  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
  - nvidia,edid: supplies a binary EDID blob
  - nvidia,panel: phandle of a display panel

- hdmi: High Definition Multimedia Interface

  Required properties:
  - compatible: "nvidia,tegra<chip>-hdmi"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - hdmi-supply: supply for the +5V HDMI connector pin
  - vdd-supply: regulator for supply voltage
  - pll-supply: regulator for PLL
  - clocks: Must contain an entry for each entry in clock-names.
    See ../clocks/clock-bindings.txt for details.
  - clock-names: Must include the following entries:
    - hdmi
      This MUST be the first entry.
    - parent
  - resets: Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.
  - reset-names: Must include the following entries:
    - hdmi

  Optional properties:
  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
  - nvidia,edid: supplies a binary EDID blob
  - nvidia,panel: phandle of a display panel

- tvo: TV encoder output

  Required properties:
  - compatible: "nvidia,tegra<chip>-tvo"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain one entry, for the module clock.
    See ../clocks/clock-bindings.txt for details.

- dsi: display serial interface

  Required properties:
  - compatible: "nvidia,tegra<chip>-dsi"
  - reg: Physical base address and length of the controller's registers.
  - clocks: Must contain an entry for each entry in clock-names.
    See ../clocks/clock-bindings.txt for details.
  - clock-names: Must include the following entries:
    - dsi
      This MUST be the first entry.
    - lp
    - parent
  - resets: Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.
  - reset-names: Must include the following entries:
    - dsi
  - avdd-dsi-supply: phandle of a supply that powers the DSI controller
  - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
    which pads are used by this DSI output and need to be calibrated. See also
    ../display/tegra/nvidia,tegra114-mipi.txt.

  Optional properties:
  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
  - nvidia,edid: supplies a binary EDID blob
  - nvidia,panel: phandle of a display panel
  - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang
    up with in order to support up to 8 data lanes

- sor: serial output resource

  Required properties:
  - compatible: Should be:
    - "nvidia,tegra124-sor": for Tegra124 and Tegra132
    - "nvidia,tegra132-sor": for Tegra132
    - "nvidia,tegra210-sor": for Tegra210
    - "nvidia,tegra210-sor1": for Tegra210
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain an entry for each entry in clock-names.
    See ../clocks/clock-bindings.txt for details.
  - clock-names: Must include the following entries:
    - sor: clock input for the SOR hardware
    - source: source clock for the SOR clock
    - parent: input for the pixel clock
    - dp: reference clock for the SOR clock
    - safe: safe reference for the SOR clock during power up
  - resets: Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.
  - reset-names: Must include the following entries:
    - sor

  Optional properties:
  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
  - nvidia,edid: supplies a binary EDID blob
  - nvidia,panel: phandle of a display panel

  Optional properties when driving an eDP output:
  - nvidia,dpaux: phandle to a DispayPort AUX interface

- dpaux: DisplayPort AUX interface
  - compatible : Should contain one of the following:
    - "nvidia,tegra124-dpaux": for Tegra124 and Tegra132
    - "nvidia,tegra210-dpaux": for Tegra210
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain an entry for each entry in clock-names.
    See ../clocks/clock-bindings.txt for details.
  - clock-names: Must include the following entries:
    - dpaux: clock input for the DPAUX hardware
    - parent: reference clock
  - resets: Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.
  - reset-names: Must include the following entries:
    - dpaux
  - vdd-supply: phandle of a supply that powers the DisplayPort link
  - i2c-bus: Subnode where I2C slave devices are listed. This subnode
    must be always present. If there are no I2C slave devices, an empty
    node should be added. See ../../i2c/i2c.txt for more information.

  See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information
  regarding the DPAUX pad controller bindings.

Example:

/ {
	...

	host1x {
		compatible = "nvidia,tegra20-host1x", "simple-bus";
		reg = <0x50000000 0x00024000>;
		interrupts = <0 65 0x04   /* mpcore syncpt */
			      0 67 0x04>; /* mpcore general */
		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
		resets = <&tegra_car 28>;
		reset-names = "host1x";

		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x54000000 0x54000000 0x04000000>;

		mpe {
			compatible = "nvidia,tegra20-mpe";
			reg = <0x54040000 0x00040000>;
			interrupts = <0 68 0x04>;
			clocks = <&tegra_car TEGRA20_CLK_MPE>;
			resets = <&tegra_car 60>;
			reset-names = "mpe";
		};

		vi {
			compatible = "nvidia,tegra20-vi";
			reg = <0x54080000 0x00040000>;
			interrupts = <0 69 0x04>;
			clocks = <&tegra_car TEGRA20_CLK_VI>;
			resets = <&tegra_car 100>;
			reset-names = "vi";
		};

		epp {
			compatible = "nvidia,tegra20-epp";
			reg = <0x540c0000 0x00040000>;
			interrupts = <0 70 0x04>;
			clocks = <&tegra_car TEGRA20_CLK_EPP>;
			resets = <&tegra_car 19>;
			reset-names = "epp";
		};

		isp {
			compatible = "nvidia,tegra20-isp";
			reg = <0x54100000 0x00040000>;
			interrupts = <0 71 0x04>;
			clocks = <&tegra_car TEGRA20_CLK_ISP>;
			resets = <&tegra_car 23>;
			reset-names = "isp";
		};

		gr2d {
			compatible = "nvidia,tegra20-gr2d";
			reg = <0x54140000 0x00040000>;
			interrupts = <0 72 0x04>;
			clocks = <&tegra_car TEGRA20_CLK_GR2D>;
			resets = <&tegra_car 21>;
			reset-names = "2d";
		};

		gr3d {
			compatible = "nvidia,tegra20-gr3d";
			reg = <0x54180000 0x00040000>;
			clocks = <&tegra_car TEGRA20_CLK_GR3D>;
			resets = <&tegra_car 24>;
			reset-names = "3d";
		};

		dc@54200000 {
			compatible = "nvidia,tegra20-dc";
			reg = <0x54200000 0x00040000>;
			interrupts = <0 73 0x04>;
			clocks = <&tegra_car TEGRA20_CLK_DISP1>,
				 <&tegra_car TEGRA20_CLK_PLL_P>;
			clock-names = "dc", "parent";
			resets = <&tegra_car 27>;
			reset-names = "dc";

			rgb {
				status = "disabled";
			};
		};

		dc@54240000 {
			compatible = "nvidia,tegra20-dc";
			reg = <0x54240000 0x00040000>;
			interrupts = <0 74 0x04>;
			clocks = <&tegra_car TEGRA20_CLK_DISP2>,
				 <&tegra_car TEGRA20_CLK_PLL_P>;
			clock-names = "dc", "parent";
			resets = <&tegra_car 26>;
			reset-names = "dc";

			rgb {
				status = "disabled";
			};
		};

		hdmi {
			compatible = "nvidia,tegra20-hdmi";
			reg = <0x54280000 0x00040000>;
			interrupts = <0 75 0x04>;
			clocks = <&tegra_car TEGRA20_CLK_HDMI>,
				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
			clock-names = "hdmi", "parent";
			resets = <&tegra_car 51>;
			reset-names = "hdmi";
			status = "disabled";
		};

		tvo {
			compatible = "nvidia,tegra20-tvo";
			reg = <0x542c0000 0x00040000>;
			interrupts = <0 76 0x04>;
			clocks = <&tegra_car TEGRA20_CLK_TVO>;
			status = "disabled";
		};

		dsi {
			compatible = "nvidia,tegra20-dsi";
			reg = <0x54300000 0x00040000>;
			clocks = <&tegra_car TEGRA20_CLK_DSI>,
				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
			clock-names = "dsi", "parent";
			resets = <&tegra_car 48>;
			reset-names = "dsi";
			status = "disabled";
		};
	};

	...
};
Commit	Line	Data
d8f4a9ed TR	1	NVIDIA Tegra host1x
	2
	3	Required properties:
	4	- compatible: "nvidia,tegra<chip>-host1x"
	5	- reg: Physical base address and length of the controller's registers.
	6	- interrupts: The interrupt outputs from the controller.
	7	- #address-cells: The number of cells used to represent physical base addresses
	8	in the host1x address space. Should be 1.
	9	- #size-cells: The number of cells used to represent the size of an address
	10	range in the host1x address space. Should be 1.
	11	- ranges: The mapping of the host1x address space to the CPU address space.
d8f64797 SW	12	- clocks: Must contain one entry, for the module clock.
d8f64797 SW	13	See ../clocks/clock-bindings.txt for details.
07999587 SW	14	- resets: Must contain an entry for each entry in reset-names.
	15	See ../reset/reset.txt for details.
	16	- reset-names: Must include the following entries:
	17	- host1x
d8f4a9ed TR	18
	19	The host1x top-level node defines a number of children, each representing one
	20	of the following host1x client modules:
	21
	22	- mpe: video encoder
	23
	24	Required properties:
	25	- compatible: "nvidia,tegra<chip>-mpe"
	26	- reg: Physical base address and length of the controller's registers.
	27	- interrupts: The interrupt outputs from the controller.
d8f64797 SW	28	- clocks: Must contain one entry, for the module clock.
d8f64797 SW	29	See ../clocks/clock-bindings.txt for details.
07999587 SW	30	- resets: Must contain an entry for each entry in reset-names.
	31	See ../reset/reset.txt for details.
	32	- reset-names: Must include the following entries:
	33	- mpe
d8f4a9ed TR	34
	35	- vi: video input
	36
	37	Required properties:
	38	- compatible: "nvidia,tegra<chip>-vi"
	39	- reg: Physical base address and length of the controller's registers.
	40	- interrupts: The interrupt outputs from the controller.
d8f64797 SW	41	- clocks: Must contain one entry, for the module clock.
d8f64797 SW	42	See ../clocks/clock-bindings.txt for details.
07999587 SW	43	- resets: Must contain an entry for each entry in reset-names.
	44	See ../reset/reset.txt for details.
	45	- reset-names: Must include the following entries:
	46	- vi
d8f4a9ed TR	47
	48	- epp: encoder pre-processor
	49
	50	Required properties:
	51	- compatible: "nvidia,tegra<chip>-epp"
	52	- reg: Physical base address and length of the controller's registers.
	53	- interrupts: The interrupt outputs from the controller.
d8f64797 SW	54	- clocks: Must contain one entry, for the module clock.
d8f64797 SW	55	See ../clocks/clock-bindings.txt for details.
07999587 SW	56	- resets: Must contain an entry for each entry in reset-names.
	57	See ../reset/reset.txt for details.
	58	- reset-names: Must include the following entries:
	59	- epp
d8f4a9ed TR	60
	61	- isp: image signal processor
	62
	63	Required properties:
	64	- compatible: "nvidia,tegra<chip>-isp"
	65	- reg: Physical base address and length of the controller's registers.
	66	- interrupts: The interrupt outputs from the controller.
d8f64797 SW	67	- clocks: Must contain one entry, for the module clock.
d8f64797 SW	68	See ../clocks/clock-bindings.txt for details.
07999587 SW	69	- resets: Must contain an entry for each entry in reset-names.
	70	See ../reset/reset.txt for details.
	71	- reset-names: Must include the following entries:
	72	- isp
d8f4a9ed TR	73
	74	- gr2d: 2D graphics engine
	75
	76	Required properties:
	77	- compatible: "nvidia,tegra<chip>-gr2d"
	78	- reg: Physical base address and length of the controller's registers.
	79	- interrupts: The interrupt outputs from the controller.
d8f64797 SW	80	- clocks: Must contain one entry, for the module clock.
d8f64797 SW	81	See ../clocks/clock-bindings.txt for details.
07999587 SW	82	- resets: Must contain an entry for each entry in reset-names.
	83	See ../reset/reset.txt for details.
	84	- reset-names: Must include the following entries:
	85	- 2d
d8f4a9ed TR	86
	87	- gr3d: 3D graphics engine
	88
	89	Required properties:
	90	- compatible: "nvidia,tegra<chip>-gr3d"
	91	- reg: Physical base address and length of the controller's registers.
d8f64797 SW	92	- clocks: Must contain an entry for each entry in clock-names.
	93	See ../clocks/clock-bindings.txt for details.
	94	- clock-names: Must include the following entries:
	95	(This property may be omitted if the only clock in the list is "3d")
	96	- 3d
	97	This MUST be the first entry.
	98	- 3d2 (Only required on SoCs with two 3D clocks)
07999587 SW	99	- resets: Must contain an entry for each entry in reset-names.
	100	See ../reset/reset.txt for details.
	101	- reset-names: Must include the following entries:
	102	- 3d
	103	- 3d2 (Only required on SoCs with two 3D clocks)
d8f4a9ed TR	104
	105	- dc: display controller
	106
	107	Required properties:
	108	- compatible: "nvidia,tegra<chip>-dc"
	109	- reg: Physical base address and length of the controller's registers.
	110	- interrupts: The interrupt outputs from the controller.
d8f64797 SW	111	- clocks: Must contain an entry for each entry in clock-names.
	112	See ../clocks/clock-bindings.txt for details.
	113	- clock-names: Must include the following entries:
	114	- dc
	115	This MUST be the first entry.
	116	- parent
07999587 SW	117	- resets: Must contain an entry for each entry in reset-names.
	118	See ../reset/reset.txt for details.
	119	- reset-names: Must include the following entries:
	120	- dc
13411ddd TR	121	- nvidia,head: The number of the display controller head. This is used to
	122	setup the various types of output to receive video data from the given
	123	head.
d8f4a9ed TR	124
	125	Each display controller node has a child node, named "rgb", that represents
	126	the RGB output associated with the controller. It can take the following
	127	optional properties:
	128	- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
	129	- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
	130	- nvidia,edid: supplies a binary EDID blob
9be7d864	131	- nvidia,panel: phandle of a display panel
d8f4a9ed TR	132
	133	- hdmi: High Definition Multimedia Interface
	134
	135	Required properties:
	136	- compatible: "nvidia,tegra<chip>-hdmi"
	137	- reg: Physical base address and length of the controller's registers.
	138	- interrupts: The interrupt outputs from the controller.
fb50a116	139	- hdmi-supply: supply for the +5V HDMI connector pin
d8f4a9ed TR	140	- vdd-supply: regulator for supply voltage
d8f4a9ed TR	141	- pll-supply: regulator for PLL
d8f64797 SW	142	- clocks: Must contain an entry for each entry in clock-names.
	143	See ../clocks/clock-bindings.txt for details.
	144	- clock-names: Must include the following entries:
	145	- hdmi
	146	This MUST be the first entry.
	147	- parent
07999587 SW	148	- resets: Must contain an entry for each entry in reset-names.
	149	See ../reset/reset.txt for details.
	150	- reset-names: Must include the following entries:
	151	- hdmi
d8f4a9ed TR	152
	153	Optional properties:
	154	- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
	155	- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
	156	- nvidia,edid: supplies a binary EDID blob
9be7d864	157	- nvidia,panel: phandle of a display panel
d8f4a9ed TR	158
	159	- tvo: TV encoder output
	160
	161	Required properties:
	162	- compatible: "nvidia,tegra<chip>-tvo"
	163	- reg: Physical base address and length of the controller's registers.
	164	- interrupts: The interrupt outputs from the controller.
d8f64797 SW	165	- clocks: Must contain one entry, for the module clock.
d8f64797 SW	166	See ../clocks/clock-bindings.txt for details.
d8f4a9ed TR	167
	168	- dsi: display serial interface
	169
	170	Required properties:
	171	- compatible: "nvidia,tegra<chip>-dsi"
	172	- reg: Physical base address and length of the controller's registers.
d8f64797 SW	173	- clocks: Must contain an entry for each entry in clock-names.
	174	See ../clocks/clock-bindings.txt for details.
	175	- clock-names: Must include the following entries:
	176	- dsi
	177	This MUST be the first entry.
dec72739	178	- lp
d8f64797	179	- parent
07999587 SW	180	- resets: Must contain an entry for each entry in reset-names.
	181	See ../reset/reset.txt for details.
	182	- reset-names: Must include the following entries:
	183	- dsi
3b077afb	184	- avdd-dsi-supply: phandle of a supply that powers the DSI controller
dec72739 TR	185	- nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
dec72739 TR	186	which pads are used by this DSI output and need to be calibrated. See also
efdbd734	187	../display/tegra/nvidia,tegra114-mipi.txt.
dec72739 TR	188
	189	Optional properties:
	190	- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
	191	- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
	192	- nvidia,edid: supplies a binary EDID blob
	193	- nvidia,panel: phandle of a display panel
e94236cd TR	194	- nvidia,ganged-mode: contains a phandle to a second DSI controller to gang
e94236cd TR	195	up with in order to support up to 8 data lanes
d8f4a9ed	196
6b6b6042 TR	197	- sor: serial output resource
	198
	199	Required properties:
3309ac83 TR	200	- compatible: Should be:
	201	- "nvidia,tegra124-sor": for Tegra124 and Tegra132
	202	- "nvidia,tegra132-sor": for Tegra132
	203	- "nvidia,tegra210-sor": for Tegra210
459cc2c6	204	- "nvidia,tegra210-sor1": for Tegra210
6b6b6042 TR	205	- reg: Physical base address and length of the controller's registers.
	206	- interrupts: The interrupt outputs from the controller.
	207	- clocks: Must contain an entry for each entry in clock-names.
	208	See ../clocks/clock-bindings.txt for details.
	209	- clock-names: Must include the following entries:
	210	- sor: clock input for the SOR hardware
5d2304c1	211	- source: source clock for the SOR clock
6b6b6042 TR	212	- parent: input for the pixel clock
	213	- dp: reference clock for the SOR clock
	214	- safe: safe reference for the SOR clock during power up
	215	- resets: Must contain an entry for each entry in reset-names.
	216	See ../reset/reset.txt for details.
	217	- reset-names: Must include the following entries:
	218	- sor
	219
	220	Optional properties:
	221	- nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
	222	- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
	223	- nvidia,edid: supplies a binary EDID blob
	224	- nvidia,panel: phandle of a display panel
	225
	226	Optional properties when driving an eDP output:
	227	- nvidia,dpaux: phandle to a DispayPort AUX interface
	228
	229	- dpaux: DisplayPort AUX interface
caf8a6c4 JH	230	- compatible : Should contain one of the following:
	231	- "nvidia,tegra124-dpaux": for Tegra124 and Tegra132
	232	- "nvidia,tegra210-dpaux": for Tegra210
6b6b6042 TR	233	- reg: Physical base address and length of the controller's registers.
	234	- interrupts: The interrupt outputs from the controller.
	235	- clocks: Must contain an entry for each entry in clock-names.
	236	See ../clocks/clock-bindings.txt for details.
	237	- clock-names: Must include the following entries:
	238	- dpaux: clock input for the DPAUX hardware
	239	- parent: reference clock
	240	- resets: Must contain an entry for each entry in reset-names.
	241	See ../reset/reset.txt for details.
	242	- reset-names: Must include the following entries:
	243	- dpaux
	244	- vdd-supply: phandle of a supply that powers the DisplayPort link
6cb68e46 JH	245	- i2c-bus: Subnode where I2C slave devices are listed. This subnode
	246	must be always present. If there are no I2C slave devices, an empty
	247	node should be added. See ../../i2c/i2c.txt for more information.
	248
	249	See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information
	250	regarding the DPAUX pad controller bindings.
6b6b6042	251
d8f4a9ed TR	252	Example:
	253
	254	/ {
	255	...
	256
	257	host1x {
	258	compatible = "nvidia,tegra20-host1x", "simple-bus";
	259	reg = <0x50000000 0x00024000>;
	260	interrupts = <0 65 0x04 /* mpcore syncpt */
	261	0 67 0x04>; /* mpcore general */
d8f64797	262	clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
07999587 SW	263	resets = <&tegra_car 28>;
07999587 SW	264	reset-names = "host1x";
d8f4a9ed TR	265
	266	#address-cells = <1>;
	267	#size-cells = <1>;
	268
	269	ranges = <0x54000000 0x54000000 0x04000000>;
	270
	271	mpe {
	272	compatible = "nvidia,tegra20-mpe";
	273	reg = <0x54040000 0x00040000>;
	274	interrupts = <0 68 0x04>;
d8f64797	275	clocks = <&tegra_car TEGRA20_CLK_MPE>;
07999587 SW	276	resets = <&tegra_car 60>;
07999587 SW	277	reset-names = "mpe";
d8f4a9ed TR	278	};
	279
	280	vi {
	281	compatible = "nvidia,tegra20-vi";
	282	reg = <0x54080000 0x00040000>;
	283	interrupts = <0 69 0x04>;
d8f64797	284	clocks = <&tegra_car TEGRA20_CLK_VI>;
07999587 SW	285	resets = <&tegra_car 100>;
07999587 SW	286	reset-names = "vi";
d8f4a9ed TR	287	};
	288
	289	epp {
	290	compatible = "nvidia,tegra20-epp";
	291	reg = <0x540c0000 0x00040000>;
	292	interrupts = <0 70 0x04>;
d8f64797	293	clocks = <&tegra_car TEGRA20_CLK_EPP>;
07999587 SW	294	resets = <&tegra_car 19>;
07999587 SW	295	reset-names = "epp";
d8f4a9ed TR	296	};
	297
	298	isp {
	299	compatible = "nvidia,tegra20-isp";
	300	reg = <0x54100000 0x00040000>;
	301	interrupts = <0 71 0x04>;
d8f64797	302	clocks = <&tegra_car TEGRA20_CLK_ISP>;
07999587 SW	303	resets = <&tegra_car 23>;
07999587 SW	304	reset-names = "isp";
d8f4a9ed TR	305	};
	306
	307	gr2d {
	308	compatible = "nvidia,tegra20-gr2d";
	309	reg = <0x54140000 0x00040000>;
	310	interrupts = <0 72 0x04>;
d8f64797	311	clocks = <&tegra_car TEGRA20_CLK_GR2D>;
07999587 SW	312	resets = <&tegra_car 21>;
07999587 SW	313	reset-names = "2d";
d8f4a9ed TR	314	};
	315
	316	gr3d {
	317	compatible = "nvidia,tegra20-gr3d";
	318	reg = <0x54180000 0x00040000>;
d8f64797	319	clocks = <&tegra_car TEGRA20_CLK_GR3D>;
07999587 SW	320	resets = <&tegra_car 24>;
07999587 SW	321	reset-names = "3d";
d8f4a9ed TR	322	};
	323
	324	dc@54200000 {
	325	compatible = "nvidia,tegra20-dc";
	326	reg = <0x54200000 0x00040000>;
	327	interrupts = <0 73 0x04>;
d8f64797 SW	328	clocks = <&tegra_car TEGRA20_CLK_DISP1>,
d8f64797 SW	329	<&tegra_car TEGRA20_CLK_PLL_P>;
5d30be28	330	clock-names = "dc", "parent";
07999587 SW	331	resets = <&tegra_car 27>;
07999587 SW	332	reset-names = "dc";
d8f4a9ed TR	333
	334	rgb {
	335	status = "disabled";
	336	};
	337	};
	338
	339	dc@54240000 {
	340	compatible = "nvidia,tegra20-dc";
	341	reg = <0x54240000 0x00040000>;
	342	interrupts = <0 74 0x04>;
d8f64797 SW	343	clocks = <&tegra_car TEGRA20_CLK_DISP2>,
d8f64797 SW	344	<&tegra_car TEGRA20_CLK_PLL_P>;
5d30be28	345	clock-names = "dc", "parent";
07999587 SW	346	resets = <&tegra_car 26>;
07999587 SW	347	reset-names = "dc";
d8f4a9ed TR	348
	349	rgb {
	350	status = "disabled";
	351	};
	352	};
	353
	354	hdmi {
	355	compatible = "nvidia,tegra20-hdmi";
	356	reg = <0x54280000 0x00040000>;
	357	interrupts = <0 75 0x04>;
d8f64797 SW	358	clocks = <&tegra_car TEGRA20_CLK_HDMI>,
	359	<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
	360	clock-names = "hdmi", "parent";
07999587 SW	361	resets = <&tegra_car 51>;
07999587 SW	362	reset-names = "hdmi";
d8f4a9ed TR	363	status = "disabled";
	364	};
	365
	366	tvo {
	367	compatible = "nvidia,tegra20-tvo";
	368	reg = <0x542c0000 0x00040000>;
	369	interrupts = <0 76 0x04>;
d8f64797	370	clocks = <&tegra_car TEGRA20_CLK_TVO>;
d8f4a9ed TR	371	status = "disabled";
	372	};
	373
	374	dsi {
	375	compatible = "nvidia,tegra20-dsi";
	376	reg = <0x54300000 0x00040000>;
d8f64797 SW	377	clocks = <&tegra_car TEGRA20_CLK_DSI>,
	378	<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
	379	clock-names = "dsi", "parent";
07999587 SW	380	resets = <&tegra_car 48>;
07999587 SW	381	reset-names = "dsi";
d8f4a9ed TR	382	status = "disabled";
	383	};
	384	};
	385
	386	...
	387	};