Commit | Line | Data |
---|---|---|
8e6152bc ZG |
1 | * Hisilicon K3 DMA controller |
2 | ||
3 | See dma.txt first | |
4 | ||
5 | Required properties: | |
6 | - compatible: Should be "hisilicon,k3-dma-1.0" | |
7 | - reg: Should contain DMA registers location and length. | |
8 | - interrupts: Should contain one interrupt shared by all channel | |
9 | - #dma-cells: see dma.txt, should be 1, para number | |
10 | - dma-channels: physical channels supported | |
11 | - dma-requests: virtual channels supported, each virtual channel | |
12 | have specific request line | |
13 | - clocks: clock required | |
14 | ||
15 | Example: | |
16 | ||
17 | Controller: | |
18 | dma0: dma@fcd02000 { | |
19 | compatible = "hisilicon,k3-dma-1.0"; | |
20 | reg = <0xfcd02000 0x1000>; | |
21 | #dma-cells = <1>; | |
22 | dma-channels = <16>; | |
23 | dma-requests = <27>; | |
24 | interrupts = <0 12 4>; | |
25 | clocks = <&pclk>; | |
26 | status = "disable"; | |
27 | }; | |
28 | ||
29 | Client: | |
30 | Use specific request line passing from dmax | |
31 | For example, i2c0 read channel request line is 18, while write channel use 19 | |
32 | ||
33 | i2c0: i2c@fcb08000 { | |
34 | compatible = "snps,designware-i2c"; | |
35 | dmas = <&dma0 18 /* read channel */ | |
36 | &dma0 19>; /* write channel */ | |
37 | dma-names = "rx", "tx"; | |
38 | }; | |
39 | ||
40 | i2c1: i2c@fcb09000 { | |
41 | compatible = "snps,designware-i2c"; | |
42 | dmas = <&dma0 20 /* read channel */ | |
43 | &dma0 21>; /* write channel */ | |
44 | dma-names = "rx", "tx"; | |
45 | }; | |
46 |