projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 67eacc15 GL |
1 | * SHDMA Device Tree bindings |
| 2 | ||
| 3 | Sh-/r-mobile and r-car systems often have multiple identical DMA controller | |
| 4 | instances, capable of serving any of a common set of DMA slave devices, using | |
| 5 | the same configuration. To describe this topology we require all compatible | |
| 6 | SHDMA DT nodes to be placed under a DMA multiplexer node. All such compatible | |
| 7 | DMAC instances have the same number of channels and use the same DMA | |
| 8 | descriptors. Therefore respective DMA DT bindings can also all be placed in the | |
| 9 | multiplexer node. Even if there is only one such DMAC instance on a system, it | |
| 10 | still has to be placed under such a multiplexer node. | |
| 11 | ||
| 12 | * DMA multiplexer | |
| 13 | ||
| 14 | Required properties: | |
| 15 | - compatible: should be "renesas,shdma-mux" | |
| 16 | - #dma-cells: should be <1>, see "dmas" property below | |
| 17 | ||
| 18 | Optional properties (currently unused): | |
| 19 | - dma-channels: number of DMA channels | |
| 20 | - dma-requests: number of DMA request signals | |
| 21 | ||
| 22 | * DMA controller | |
| 23 | ||
| 24 | Required properties: | |
| 4981c4dc GL |
25 | - compatible: should be of the form "renesas,shdma-<soc>", where <soc> should |
| 26 | be replaced with the desired SoC model, e.g. | |
| 27 | "renesas,shdma-r8a73a4" for the system DMAC on r8a73a4 SoC | |
| 67eacc15 GL |
28 | |
| 29 | Example: | |
| 4981c4dc | 30 | dmac: dma-multiplexer@0 { |
| 67eacc15 GL |
31 | compatible = "renesas,shdma-mux"; |
| 32 | #dma-cells = <1>; | |
| 4981c4dc | 33 | dma-channels = <20>; |
| 67eacc15 | 34 | dma-requests = <256>; |
| 4981c4dc GL |
35 | #address-cells = <2>; |
| 36 | #size-cells = <2>; | |
| 67eacc15 GL |
37 | ranges; |
| 38 | ||
| 4981c4dc GL |
39 | dma0: dma-controller@e6700020 { |
| 40 | compatible = "renesas,shdma-r8a73a4"; | |
| 41 | reg = <0 0xe6700020 0 0x89e0>; | |
| 67eacc15 | 42 | interrupt-parent = <&gic>; |
| 4981c4dc GL |
43 | interrupts = <0 220 4 |
| 44 | 0 200 4 | |
| 45 | 0 201 4 | |
| 46 | 0 202 4 | |
| 47 | 0 203 4 | |
| 48 | 0 204 4 | |
| 49 | 0 205 4 | |
| 50 | 0 206 4 | |
| 51 | 0 207 4 | |
| 52 | 0 208 4 | |
| 53 | 0 209 4 | |
| 54 | 0 210 4 | |
| 55 | 0 211 4 | |
| 56 | 0 212 4 | |
| 57 | 0 213 4 | |
| 58 | 0 214 4 | |
| 59 | 0 215 4 | |
| 60 | 0 216 4 | |
| 61 | 0 217 4 | |
| 62 | 0 218 4 | |
| 63 | 0 219 4>; | |
| 67eacc15 GL |
64 | interrupt-names = "error", |
| 65 | "ch0", "ch1", "ch2", "ch3", | |
| 4981c4dc GL |
66 | "ch4", "ch5", "ch6", "ch7", |
| 67 | "ch8", "ch9", "ch10", "ch11", | |
| 68 | "ch12", "ch13", "ch14", "ch15", | |
| 69 | "ch16", "ch17", "ch18", "ch19"; | |
| 67eacc15 GL |
70 | }; |
| 71 | }; | |
| 72 | ||
| 73 | * DMA client | |
| 74 | ||
| 75 | Required properties: | |
| 76 | - dmas: a list of <[DMA multiplexer phandle] [MID/RID value]> pairs, | |
| 77 | where MID/RID values are fixed handles, specified in the SoC | |
| 78 | manual | |
| 79 | - dma-names: a list of DMA channel names, one per "dmas" entry | |
| 80 | ||
| 81 | Example: | |
| 82 | dmas = <&dmac 0xd1 | |
| 83 | &dmac 0xd2>; | |
| 84 | dma-names = "tx", "rx"; |