projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| d3f797d9 VK |
1 | * Synopsys Designware DMA Controller |
| 2 | ||
| 3 | Required properties: | |
| 4 | - compatible: "snps,dma-spear1340" | |
| 5 | - reg: Address range of the DMAC registers | |
| d3f797d9 | 6 | - interrupt: Should contain the DMAC interrupt number |
| f9c6a655 AB |
7 | - dma-channels: Number of channels supported by hardware |
| 8 | - dma-requests: Number of DMA request lines supported, up to 16 | |
| 9 | - dma-masters: Number of AHB masters supported by the controller | |
| 10 | - #dma-cells: must be <3> | |
| a9ddb575 VK |
11 | - chan_allocation_order: order of allocation of channel, 0 (default): ascending, |
| 12 | 1: descending | |
| 13 | - chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1: | |
| 14 | increase from chan n->0 | |
| 15 | - block_size: Maximum block size supported by the controller | |
| 2e65060e AS |
16 | - data-width: Maximum data width supported by hardware per AHB master |
| 17 | (in bytes, power of 2) | |
| 18 | ||
| 19 | ||
| 20 | Deprecated properties: | |
| a9ddb575 VK |
21 | - data_width: Maximum data width supported by hardware per AHB master |
| 22 | (0 - 8bits, 1 - 16bits, ..., 5 - 256bits) | |
| f9c6a655 AB |
23 | |
| 24 | ||
| 25 | Optional properties: | |
| 26 | - interrupt-parent: Should be the phandle for the interrupt controller | |
| 27 | that services interrupts for this device | |
| 28 | - is_private: The device channels should be marked as private and not for by the | |
| 29 | general purpose DMA channel allocator. False if not passed. | |
| d3f797d9 VK |
30 | |
| 31 | Example: | |
| 32 | ||
| f9c6a655 | 33 | dmahost: dma@fc000000 { |
| d3f797d9 VK |
34 | compatible = "snps,dma-spear1340"; |
| 35 | reg = <0xfc000000 0x1000>; | |
| 36 | interrupt-parent = <&vic1>; | |
| 37 | interrupts = <12>; | |
| a9ddb575 | 38 | |
| f9c6a655 AB |
39 | dma-channels = <8>; |
| 40 | dma-requests = <16>; | |
| 41 | dma-masters = <2>; | |
| 42 | #dma-cells = <3>; | |
| a9ddb575 VK |
43 | chan_allocation_order = <1>; |
| 44 | chan_priority = <1>; | |
| 45 | block_size = <0xfff>; | |
| 2e65060e | 46 | data-width = <8 8>; |
| f9c6a655 | 47 | }; |
| a9ddb575 | 48 | |
| f9c6a655 AB |
49 | DMA clients connected to the Designware DMA controller must use the format |
| 50 | described in the dma.txt file, using a four-cell specifier for each channel. | |
| 51 | The four cells in order are: | |
| 52 | ||
| 53 | 1. A phandle pointing to the DMA controller | |
| 54 | 2. The DMA request line number | |
| c422025c AS |
55 | 3. Memory master for transfers on allocated channel |
| 56 | 4. Peripheral master for transfers on allocated channel | |
| f9c6a655 AB |
57 | |
| 58 | Example: | |
| 59 | ||
| 60 | serial@e0000000 { | |
| 61 | compatible = "arm,pl011", "arm,primecell"; | |
| 62 | reg = <0xe0000000 0x1000>; | |
| 63 | interrupts = <0 35 0x4>; | |
| 64 | status = "disabled"; | |
| 65 | dmas = <&dmahost 12 0 1>, | |
| 66 | <&dmahost 13 0 1 0>; | |
| 67 | dma-names = "rx", "rx"; | |
| d3f797d9 | 68 | }; |