Commit | Line | Data |
---|---|---|
fa332de5 LJ |
1 | * DMA40 DMA Controller |
2 | ||
3 | Required properties: | |
4 | - compatible: "stericsson,dma40" | |
5 | - reg: Address range of the DMAC registers | |
6 | - reg-names: Names of the above areas to use during resource look-up | |
7 | - interrupt: Should contain the DMAC interrupt number | |
8 | - #dma-cells: must be <3> | |
a7dacb68 | 9 | - memcpy-channels: Channels to be used for memcpy |
fa332de5 LJ |
10 | |
11 | Optional properties: | |
12 | - dma-channels: Number of channels supported by hardware - if not present | |
13 | the driver will attempt to obtain the information from H/W | |
499c2bc3 | 14 | - disabled-channels: Channels which can not be used |
fa332de5 LJ |
15 | |
16 | Example: | |
17 | ||
18 | dma: dma-controller@801C0000 { | |
19 | compatible = "stericsson,db8500-dma40", "stericsson,dma40"; | |
20 | reg = <0x801C0000 0x1000 0x40010000 0x800>; | |
21 | reg-names = "base", "lcpa"; | |
22 | interrupt-parent = <&intc>; | |
23 | interrupts = <0 25 0x4>; | |
24 | ||
25 | #dma-cells = <2>; | |
a7dacb68 | 26 | memcpy-channels = <56 57 58 59 60>; |
499c2bc3 | 27 | disabled-channels = <12>; |
fa332de5 LJ |
28 | dma-channels = <8>; |
29 | }; | |
30 | ||
31 | Clients | |
32 | Required properties: | |
33 | - dmas: Comma separated list of dma channel requests | |
34 | - dma-names: Names of the aforementioned requested channels | |
35 | ||
36 | Each dmas request consists of 4 cells: | |
37 | 1. A phandle pointing to the DMA controller | |
f60f141c LW |
38 | 2. Device signal number, the signal line for single and burst requests |
39 | connected from the device to the DMA40 engine | |
fa332de5 | 40 | 3. The DMA request line number (only when 'use fixed channel' is set) |
f60f141c LW |
41 | 4. A 32bit mask specifying; mode, direction and endianness |
42 | [NB: This list will grow] | |
fa332de5 LJ |
43 | 0x00000001: Mode: |
44 | Logical channel when unset | |
45 | Physical channel when set | |
46 | 0x00000002: Direction: | |
47 | Memory to Device when unset | |
48 | Device to Memory when set | |
9ca18397 | 49 | 0x00000004: Endianness: |
fa332de5 LJ |
50 | Little endian when unset |
51 | Big endian when set | |
52 | 0x00000008: Use fixed channel: | |
53 | Use automatic channel selection when unset | |
54 | Use DMA request line number when set | |
0a05ef0e LJ |
55 | 0x00000010: Set channel as high priority: |
56 | Normal priority when unset | |
57 | High priority when set | |
fa332de5 | 58 | |
f60f141c LW |
59 | Existing signal numbers for the DB8500 ASIC. Unless specified, the signals are |
60 | bidirectional, i.e. the same for RX and TX operations: | |
61 | ||
62 | 0: SPI controller 0 | |
63 | 1: SD/MMC controller 0 (unused) | |
64 | 2: SD/MMC controller 1 (unused) | |
65 | 3: SD/MMC controller 2 (unused) | |
66 | 4: I2C port 1 | |
67 | 5: I2C port 3 | |
68 | 6: I2C port 2 | |
69 | 7: I2C port 4 | |
70 | 8: Synchronous Serial Port SSP0 | |
71 | 9: Synchronous Serial Port SSP1 | |
72 | 10: Multi-Channel Display Engine MCDE RX | |
73 | 11: UART port 2 | |
74 | 12: UART port 1 | |
75 | 13: UART port 0 | |
76 | 14: Multirate Serial Port MSP2 | |
77 | 15: I2C port 0 | |
78 | 16: USB OTG in/out endpoints 7 & 15 | |
79 | 17: USB OTG in/out endpoints 6 & 14 | |
80 | 18: USB OTG in/out endpoints 5 & 13 | |
81 | 19: USB OTG in/out endpoints 4 & 12 | |
82 | 20: SLIMbus or HSI channel 0 | |
83 | 21: SLIMbus or HSI channel 1 | |
84 | 22: SLIMbus or HSI channel 2 | |
85 | 23: SLIMbus or HSI channel 3 | |
86 | 24: Multimedia DSP SXA0 | |
87 | 25: Multimedia DSP SXA1 | |
88 | 26: Multimedia DSP SXA2 | |
89 | 27: Multimedia DSP SXA3 | |
90 | 28: SD/MM controller 2 | |
91 | 29: SD/MM controller 0 | |
92 | 30: MSP port 1 on DB8500 v1, MSP port 3 on DB8500 v2 | |
93 | 31: MSP port 0 or SLIMbus channel 0 | |
94 | 32: SD/MM controller 1 | |
95 | 33: SPI controller 2 | |
96 | 34: i2c3 RX2 TX2 | |
97 | 35: SPI controller 1 | |
98 | 36: USB OTG in/out endpoints 3 & 11 | |
99 | 37: USB OTG in/out endpoints 2 & 10 | |
100 | 38: USB OTG in/out endpoints 1 & 9 | |
101 | 39: USB OTG in/out endpoints 8 | |
102 | 40: SPI controller 3 | |
103 | 41: SD/MM controller 3 | |
104 | 42: SD/MM controller 4 | |
105 | 43: SD/MM controller 5 | |
106 | 44: Multimedia DSP SXA4 | |
107 | 45: Multimedia DSP SXA5 | |
108 | 46: SLIMbus channel 8 or Multimedia DSP SXA6 | |
109 | 47: SLIMbus channel 9 or Multimedia DSP SXA7 | |
110 | 48: Crypto Accelerator 1 | |
111 | 49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX | |
112 | 50: Hash Accelerator 1 TX | |
113 | 51: memcpy TX (to be used by the DMA driver for memcpy operations) | |
114 | 52: SLIMbus or HSI channel 4 | |
115 | 53: SLIMbus or HSI channel 5 | |
116 | 54: SLIMbus or HSI channel 6 | |
117 | 55: SLIMbus or HSI channel 7 | |
118 | 56: memcpy (to be used by the DMA driver for memcpy operations) | |
119 | 57: memcpy (to be used by the DMA driver for memcpy operations) | |
120 | 58: memcpy (to be used by the DMA driver for memcpy operations) | |
121 | 59: memcpy (to be used by the DMA driver for memcpy operations) | |
122 | 60: memcpy (to be used by the DMA driver for memcpy operations) | |
123 | 61: Crypto Accelerator 0 | |
124 | 62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX | |
125 | 63: Hash Accelerator 0 TX | |
126 | ||
fa332de5 LJ |
127 | Example: |
128 | ||
129 | uart@80120000 { | |
130 | compatible = "arm,pl011", "arm,primecell"; | |
131 | reg = <0x80120000 0x1000>; | |
132 | interrupts = <0 11 0x4>; | |
133 | ||
134 | dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */ | |
135 | <&dma 13 0 0x0>; /* Logical - MemToDev */ | |
136 | dma-names = "rx", "rx"; | |
137 | ||
138 | status = "disabled"; | |
139 | }; |