[deliverable/linux.git] / Documentation / devicetree / bindings / dma / stm32-dma.txt

* STMicroelectronics STM32 DMA controller

The STM32 DMA is a general-purpose direct memory access controller capable of
supporting 8 independent DMA channels. Each channel can have up to 8 requests.

Required properties:
- compatible: Should be "st,stm32-dma"
- reg: Should contain DMA registers location and length. This should include
  all of the per-channel registers.
- interrupts: Should contain all of the per-channel DMA interrupts in
  ascending order with respect to the DMA channel index.
- clocks: Should contain the input clock of the DMA instance.
- #dma-cells : Must be <4>. See DMA client paragraph for more details.

Optional properties:
- resets: Reference to a reset controller asserting the DMA controller
- st,mem2mem: boolean; if defined, it indicates that the controller supports
  memory-to-memory transfer

Example:

	dma2: dma-controller@40026400 {
		compatible = "st,stm32-dma";
		reg = <0x40026400 0x400>;
		interrupts = <56>,
			     <57>,
			     <58>,
			     <59>,
			     <60>,
			     <68>,
			     <69>,
			     <70>;
		clocks = <&clk_hclk>;
		#dma-cells = <4>;
		st,mem2mem;
		resets = <&rcc 150>;
	};

* DMA client

DMA clients connected to the STM32 DMA controller must use the format
described in the dma.txt file, using a five-cell specifier for each
channel: a phandle plus four integer cells.
The four cells in order are:

1. The channel id
2. The request line number
3. A 32bit mask specifying the DMA channel configuration which are device
   dependent:
  -bit 9: Peripheral Increment Address
	0x0: no address increment between transfers
	0x1: increment address between transfers
 -bit 10: Memory Increment Address
	0x0: no address increment between transfers
	0x1: increment address between transfers
 -bit 15: Peripheral Increment Offset Size
	0x0: offset size is linked to the peripheral bus width
	0x1: offset size is fixed to 4 (32-bit alignment)
 -bit 16-17: Priority level
	0x0: low
	0x1: medium
	0x2: high
	0x3: very high
5. A 32bit mask specifying the DMA FIFO threshold configuration which are device
   dependent:
 -bit 0-1: Fifo threshold
	0x0: 1/4 full FIFO
	0x1: 1/2 full FIFO
	0x2: 3/4 full FIFO
	0x3: full FIFO

Example:

	usart1: serial@40011000 {
		compatible = "st,stm32-usart", "st,stm32-uart";
		reg = <0x40011000 0x400>;
		interrupts = <37>;
		clocks = <&clk_pclk2>;
		dmas = <&dma2 2 4 0x10400 0x3>,
		       <&dma2 7 5 0x10200 0x3>;
		dma-names = "rx", "tx";
	};
Commit	Line	Data
5827a4ba CM	1	* STMicroelectronics STM32 DMA controller
	2
	3	The STM32 DMA is a general-purpose direct memory access controller capable of
	4	supporting 8 independent DMA channels. Each channel can have up to 8 requests.
	5
	6	Required properties:
	7	- compatible: Should be "st,stm32-dma"
	8	- reg: Should contain DMA registers location and length. This should include
	9	all of the per-channel registers.
	10	- interrupts: Should contain all of the per-channel DMA interrupts in
	11	ascending order with respect to the DMA channel index.
	12	- clocks: Should contain the input clock of the DMA instance.
	13	- #dma-cells : Must be <4>. See DMA client paragraph for more details.
	14
	15	Optional properties:
	16	- resets: Reference to a reset controller asserting the DMA controller
	17	- st,mem2mem: boolean; if defined, it indicates that the controller supports
	18	memory-to-memory transfer
	19
	20	Example:
	21
	22	dma2: dma-controller@40026400 {
	23	compatible = "st,stm32-dma";
	24	reg = <0x40026400 0x400>;
	25	interrupts = <56>,
	26	<57>,
	27	<58>,
	28	<59>,
	29	<60>,
	30	<68>,
	31	<69>,
	32	<70>;
	33	clocks = <&clk_hclk>;
	34	#dma-cells = <4>;
	35	st,mem2mem;
	36	resets = <&rcc 150>;
	37	};
	38
	39	* DMA client
	40
	41	DMA clients connected to the STM32 DMA controller must use the format
	42	described in the dma.txt file, using a five-cell specifier for each
	43	channel: a phandle plus four integer cells.
	44	The four cells in order are:
	45
	46	1. The channel id
	47	2. The request line number
	48	3. A 32bit mask specifying the DMA channel configuration which are device
	49	dependent:
	50	-bit 9: Peripheral Increment Address
	51	0x0: no address increment between transfers
	52	0x1: increment address between transfers
	53	-bit 10: Memory Increment Address
	54	0x0: no address increment between transfers
	55	0x1: increment address between transfers
	56	-bit 15: Peripheral Increment Offset Size
	57	0x0: offset size is linked to the peripheral bus width
	58	0x1: offset size is fixed to 4 (32-bit alignment)
	59	-bit 16-17: Priority level
	60	0x0: low
	61	0x1: medium
	62	0x2: high
	63	0x3: very high
	64	5. A 32bit mask specifying the DMA FIFO threshold configuration which are device
65	dependent:
66	-bit 0-1: Fifo threshold
67	0x0: 1/4 full FIFO
68	0x1: 1/2 full FIFO
69	0x2: 3/4 full FIFO
70	0x3: full FIFO
71
72	Example:
73
74	usart1: serial@40011000 {
75	compatible = "st,stm32-usart", "st,stm32-uart";
76	reg = <0x40011000 0x400>;
77	interrupts = <37>;
78	clocks = <&clk_pclk2>;
79	dmas = <&dma2 2 4 0x10400 0x3>,
80	<&dma2 7 5 0x10200 0x3>;
81	dma-names = "rx", "tx";
82	};