Commit | Line | Data |
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3c677cc4 MR |
1 | Allwinner A31 DMA Controller |
2 | ||
3 | This driver follows the generic DMA bindings defined in dma.txt. | |
4 | ||
5 | Required properties: | |
6 | ||
f008db8c JK |
7 | - compatible: Must be one of |
8 | "allwinner,sun6i-a31-dma" | |
9 | "allwinner,sun8i-a23-dma" | |
10 | "allwinner,sun8i-h3-dma" | |
3c677cc4 MR |
11 | - reg: Should contain the registers base address and length |
12 | - interrupts: Should contain a reference to the interrupt used by this device | |
13 | - clocks: Should contain a reference to the parent AHB clock | |
14 | - resets: Should contain a reference to the reset controller asserting | |
15 | this device in reset | |
16 | - #dma-cells : Should be 1, a single cell holding a line request number | |
17 | ||
18 | Example: | |
19 | dma: dma-controller@01c02000 { | |
20 | compatible = "allwinner,sun6i-a31-dma"; | |
21 | reg = <0x01c02000 0x1000>; | |
22 | interrupts = <0 50 4>; | |
23 | clocks = <&ahb1_gates 6>; | |
24 | resets = <&ahb1_rst 6>; | |
25 | #dma-cells = <1>; | |
26 | }; | |
27 | ||
28 | Clients: | |
29 | ||
30 | DMA clients connected to the A31 DMA controller must use the format | |
31 | described in the dma.txt file, using a two-cell specifier for each | |
32 | channel: a phandle plus one integer cells. | |
33 | The two cells in order are: | |
34 | ||
35 | 1. A phandle pointing to the DMA controller. | |
36 | 2. The port ID as specified in the datasheet | |
37 | ||
38 | Example: | |
39 | spi2: spi@01c6a000 { | |
40 | compatible = "allwinner,sun6i-a31-spi"; | |
41 | reg = <0x01c6a000 0x1000>; | |
42 | interrupts = <0 67 4>; | |
43 | clocks = <&ahb1_gates 22>, <&spi2_clk>; | |
44 | clock-names = "ahb", "mod"; | |
45 | dmas = <&dma 25>, <&dma 25>; | |
46 | dma-names = "rx", "tx"; | |
47 | resets = <&ahb1_rst 22>; | |
48 | }; |