Commit | Line | Data |
---|---|---|
41e69778 RC |
1 | Qualcomm adreno/snapdragon GPU |
2 | ||
3 | Required properties: | |
4 | - compatible: "qcom,adreno-3xx" | |
5 | - reg: Physical base address and length of the controller's registers. | |
6 | - interrupts: The interrupt signal from the gpu. | |
7 | - clocks: device clocks | |
8 | See ../clocks/clock-bindings.txt for details. | |
9 | - clock-names: the following clocks are required: | |
10 | * "core_clk" | |
11 | * "iface_clk" | |
12 | * "mem_iface_clk" | |
13 | - qcom,chipid: gpu chip-id. Note this may become optional for future | |
14 | devices if we can reliably read the chipid from hw | |
15 | - qcom,gpu-pwrlevels: list of operating points | |
16 | - compatible: "qcom,gpu-pwrlevels" | |
17 | - for each qcom,gpu-pwrlevel: | |
18 | - qcom,gpu-freq: requested gpu clock speed | |
19 | - NOTE: downstream android driver defines additional parameters to | |
20 | configure memory bandwidth scaling per OPP. | |
21 | ||
22 | Example: | |
23 | ||
24 | / { | |
25 | ... | |
26 | ||
27 | gpu: qcom,kgsl-3d0@4300000 { | |
28 | compatible = "qcom,adreno-3xx"; | |
29 | reg = <0x04300000 0x20000>; | |
30 | reg-names = "kgsl_3d0_reg_memory"; | |
31 | interrupts = <GIC_SPI 80 0>; | |
32 | interrupt-names = "kgsl_3d0_irq"; | |
33 | clock-names = | |
34 | "core_clk", | |
35 | "iface_clk", | |
36 | "mem_iface_clk"; | |
37 | clocks = | |
38 | <&mmcc GFX3D_CLK>, | |
39 | <&mmcc GFX3D_AHB_CLK>, | |
40 | <&mmcc MMSS_IMEM_AHB_CLK>; | |
41 | qcom,chipid = <0x03020100>; | |
42 | qcom,gpu-pwrlevels { | |
43 | compatible = "qcom,gpu-pwrlevels"; | |
44 | qcom,gpu-pwrlevel@0 { | |
45 | qcom,gpu-freq = <450000000>; | |
46 | }; | |
47 | qcom,gpu-pwrlevel@1 { | |
48 | qcom,gpu-freq = <27000000>; | |
49 | }; | |
50 | }; | |
51 | }; | |
52 | }; |