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1 | * APM X-Gene SoC EDAC node |
2 | ||
3 | EDAC node is defined to describe on-chip error detection and correction. | |
4 | The follow error types are supported: | |
5 | ||
6 | memory controller - Memory controller | |
7 | PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache | |
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8 | L3 - L3 cache controller |
9 | SoC - SoC IP's such as Ethernet, SATA, and etc | |
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10 | |
11 | The following section describes the EDAC DT node binding. | |
12 | ||
13 | Required properties: | |
14 | - compatible : Shall be "apm,xgene-edac". | |
15 | - regmap-csw : Regmap of the CPU switch fabric (CSW) resource. | |
16 | - regmap-mcba : Regmap of the MCB-A (memory bridge) resource. | |
17 | - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource. | |
18 | - regmap-efuse : Regmap of the PMD efuse resource. | |
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19 | - regmap-rb : Regmap of the register bus resource. This property |
20 | is optional only for compatibility. If the RB | |
21 | error conditions are not cleared, it will | |
22 | continuously generate interrupt. | |
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23 | - reg : First resource shall be the CPU bus (PCP) resource. |
24 | - interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error | |
25 | IRQ(s). | |
26 | ||
27 | Required properties for memory controller subnode: | |
28 | - compatible : Shall be "apm,xgene-edac-mc". | |
29 | - reg : First resource shall be the memory controller unit | |
30 | (MCU) resource. | |
31 | - memory-controller : Instance number of the memory controller. | |
32 | ||
33 | Required properties for PMD subnode: | |
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34 | - compatible : Shall be "apm,xgene-edac-pmd" or |
35 | "apm,xgene-edac-pmd-v2". | |
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36 | - reg : First resource shall be the PMD resource. |
37 | - pmd-controller : Instance number of the PMD controller. | |
38 | ||
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39 | Required properties for L3 subnode: |
40 | - compatible : Shall be "apm,xgene-edac-l3" or | |
41 | "apm,xgene-edac-l3-v2". | |
42 | - reg : First resource shall be the L3 EDAC resource. | |
43 | ||
44 | Required properties for SoC subnode: | |
45 | - compatible : Shall be "apm,xgene-edac-soc-v1" for revision 1 or | |
46 | "apm,xgene-edac-l3-soc" for general value reporting | |
47 | only. | |
48 | - reg : First resource shall be the SoC EDAC resource. | |
49 | ||
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50 | Example: |
51 | csw: csw@7e200000 { | |
52 | compatible = "apm,xgene-csw", "syscon"; | |
53 | reg = <0x0 0x7e200000 0x0 0x1000>; | |
54 | }; | |
55 | ||
56 | mcba: mcba@7e700000 { | |
57 | compatible = "apm,xgene-mcb", "syscon"; | |
58 | reg = <0x0 0x7e700000 0x0 0x1000>; | |
59 | }; | |
60 | ||
61 | mcbb: mcbb@7e720000 { | |
62 | compatible = "apm,xgene-mcb", "syscon"; | |
63 | reg = <0x0 0x7e720000 0x0 0x1000>; | |
64 | }; | |
65 | ||
66 | efuse: efuse@1054a000 { | |
67 | compatible = "apm,xgene-efuse", "syscon"; | |
68 | reg = <0x0 0x1054a000 0x0 0x20>; | |
69 | }; | |
70 | ||
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71 | rb: rb@7e000000 { |
72 | compatible = "apm,xgene-rb", "syscon"; | |
73 | reg = <0x0 0x7e000000 0x0 0x10>; | |
74 | }; | |
75 | ||
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76 | edac@78800000 { |
77 | compatible = "apm,xgene-edac"; | |
78 | #address-cells = <2>; | |
79 | #size-cells = <2>; | |
80 | ranges; | |
81 | regmap-csw = <&csw>; | |
82 | regmap-mcba = <&mcba>; | |
83 | regmap-mcbb = <&mcbb>; | |
84 | regmap-efuse = <&efuse>; | |
5979b84d | 85 | regmap-rb = <&rb>; |
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86 | reg = <0x0 0x78800000 0x0 0x100>; |
87 | interrupts = <0x0 0x20 0x4>, | |
88 | <0x0 0x21 0x4>, | |
89 | <0x0 0x27 0x4>; | |
90 | ||
91 | edacmc@7e800000 { | |
92 | compatible = "apm,xgene-edac-mc"; | |
93 | reg = <0x0 0x7e800000 0x0 0x1000>; | |
94 | memory-controller = <0>; | |
95 | }; | |
96 | ||
97 | edacpmd@7c000000 { | |
98 | compatible = "apm,xgene-edac-pmd"; | |
99 | reg = <0x0 0x7c000000 0x0 0x200000>; | |
100 | pmd-controller = <0>; | |
101 | }; | |
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102 | |
103 | edacl3@7e600000 { | |
104 | compatible = "apm,xgene-edac-l3"; | |
105 | reg = <0x0 0x7e600000 0x0 0x1000>; | |
106 | }; | |
107 | ||
108 | edacsoc@7e930000 { | |
109 | compatible = "apm,xgene-edac-soc-v1"; | |
110 | reg = <0x0 0x7e930000 0x0 0x1000>; | |
111 | }; | |
ee66e6a2 | 112 | }; |