projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1e16dfc1 PK |
1 | GPIO controllers on MPC8xxx SoCs |
| 2 | ||
| 3 | This is for the non-QE/CPM/GUTs GPIO controllers as found on | |
| 4 | 8349, 8572, 8610 and compatible. | |
| 5 | ||
| 6 | Every GPIO controller node must have #gpio-cells property defined, | |
| 7 | this information will be used to translate gpio-specifiers. | |
| 2c0e641a GS |
8 | See bindings/gpio/gpio.txt for details of how to specify GPIO |
| 9 | information for devices. | |
| 10 | ||
| 11 | The GPIO module usually is connected to the SoC's internal interrupt | |
| 12 | controller, see bindings/interrupt-controller/interrupts.txt (the | |
| 13 | interrupt client nodes section) for details how to specify this GPIO | |
| 14 | module's interrupt. | |
| 15 | ||
| 16 | The GPIO module may serve as another interrupt controller (cascaded to | |
| 17 | the SoC's internal interrupt controller). See the interrupt controller | |
| 18 | nodes section in bindings/interrupt-controller/interrupts.txt for | |
| 19 | details. | |
| 1e16dfc1 PK |
20 | |
| 21 | Required properties: | |
| 2c0e641a GS |
22 | - compatible: "fsl,<chip>-gpio" followed by "fsl,mpc8349-gpio" |
| 23 | for 83xx, "fsl,mpc8572-gpio" for 85xx, or | |
| 24 | "fsl,mpc8610-gpio" for 86xx. | |
| 25 | - #gpio-cells: Should be two. The first cell is the pin number | |
| 26 | and the second cell is used to specify optional | |
| 27 | parameters (currently unused). | |
| 28 | - interrupt-parent: Phandle for the interrupt controller that | |
| 29 | services interrupts for this device. | |
| 30 | - interrupts: Interrupt mapping for GPIO IRQ. | |
| 31 | - gpio-controller: Marks the port as GPIO controller. | |
| 32 | ||
| 33 | Optional properties: | |
| 34 | - interrupt-controller: Empty boolean property which marks the GPIO | |
| 35 | module as an IRQ controller. | |
| 36 | - #interrupt-cells: Should be two. Defines the number of integer | |
| 37 | cells required to specify an interrupt within | |
| 38 | this interrupt controller. The first cell | |
| 39 | defines the pin number, the second cell | |
| 40 | defines additional flags (trigger type, | |
| 41 | trigger polarity). Note that the available | |
| 42 | set of trigger conditions supported by the | |
| 43 | GPIO module depends on the actual SoC. | |
| 1e16dfc1 PK |
44 | |
| 45 | Example of gpio-controller nodes for a MPC8347 SoC: | |
| 46 | ||
| 47 | gpio1: gpio-controller@c00 { | |
| 48 | #gpio-cells = <2>; | |
| 49 | compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio"; | |
| 50 | reg = <0xc00 0x100>; | |
| 1e16dfc1 | 51 | interrupt-parent = <&ipic>; |
| 2c0e641a | 52 | interrupts = <74 0x8>; |
| 1e16dfc1 | 53 | gpio-controller; |
| 2c0e641a GS |
54 | interrupt-controller; |
| 55 | #interrupt-cells = <2>; | |
| 1e16dfc1 PK |
56 | }; |
| 57 | ||
| 58 | gpio2: gpio-controller@d00 { | |
| 59 | #gpio-cells = <2>; | |
| 60 | compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio"; | |
| 61 | reg = <0xd00 0x100>; | |
| 1e16dfc1 | 62 | interrupt-parent = <&ipic>; |
| 2c0e641a | 63 | interrupts = <75 0x8>; |
| 1e16dfc1 PK |
64 | gpio-controller; |
| 65 | }; | |
| 66 | ||
| 2c0e641a | 67 | Example of a peripheral using the GPIO module as an IRQ controller: |
| 345e5c8a PK |
68 | |
| 69 | funkyfpga@0 { | |
| 70 | compatible = "funky-fpga"; | |
| 71 | ... | |
| 345e5c8a | 72 | interrupt-parent = <&gpio1>; |
| 2c0e641a | 73 | interrupts = <4 3>; |
| 345e5c8a | 74 | }; |