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| Commit | Line | Data |
|---|---|---|
| 5b7d414a GF |
1 | Broadcom STB "UPG GIO" GPIO controller |
| 2 | ||
| 3 | The controller's registers are organized as sets of eight 32-bit | |
| 4 | registers with each set controlling a bank of up to 32 pins. A single | |
| 5 | interrupt is shared for all of the banks handled by the controller. | |
| 6 | ||
| 7 | Required properties: | |
| 8 | ||
| 9 | - compatible: | |
| 10 | Must be "brcm,brcmstb-gpio" | |
| 11 | ||
| 12 | - reg: | |
| 13 | Define the base and range of the I/O address space containing | |
| 14 | the brcmstb GPIO controller registers | |
| 15 | ||
| 16 | - #gpio-cells: | |
| 17 | Should be <2>. The first cell is the pin number (within the controller's | |
| 18 | pin space), and the second is used for the following: | |
| 19 | bit[0]: polarity (0 for active-high, 1 for active-low) | |
| 20 | ||
| 21 | - gpio-controller: | |
| 22 | Specifies that the node is a GPIO controller. | |
| 23 | ||
| 24 | - brcm,gpio-bank-widths: | |
| 25 | Number of GPIO lines for each bank. Number of elements must | |
| 26 | correspond to number of banks suggested by the 'reg' property. | |
| 27 | ||
| 28 | Optional properties: | |
| 29 | ||
| 30 | - interrupts: | |
| 31 | The interrupt shared by all GPIO lines for this controller. | |
| 32 | ||
| 33 | - interrupt-parent: | |
| 34 | phandle of the parent interrupt controller | |
| 35 | ||
| 7c50181b GF |
36 | - interrupts-extended: |
| 37 | Alternate form of specifying interrupts and parents that allows for | |
| 38 | multiple parents. This takes precedence over 'interrupts' and | |
| 39 | 'interrupt-parent'. Wakeup-capable GPIO controllers often route their | |
| 40 | wakeup interrupt lines through a different interrupt controller than the | |
| 41 | primary interrupt line, making this property necessary. | |
| 42 | ||
| 5b7d414a GF |
43 | - #interrupt-cells: |
| 44 | Should be <2>. The first cell is the GPIO number, the second should specify | |
| 45 | flags. The following subset of flags is supported: | |
| 46 | - bits[3:0] trigger type and level flags | |
| 47 | 1 = low-to-high edge triggered | |
| 48 | 2 = high-to-low edge triggered | |
| 49 | 4 = active high level-sensitive | |
| 50 | 8 = active low level-sensitive | |
| 51 | Valid combinations are 1, 2, 3, 4, 8. | |
| 52 | See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt | |
| 53 | ||
| 54 | - interrupt-controller: | |
| 55 | Marks the device node as an interrupt controller | |
| 56 | ||
| 7c50181b GF |
57 | - wakeup-source: |
| 58 | GPIOs for this controller can be used as a wakeup source | |
| 5b7d414a GF |
59 | |
| 60 | Example: | |
| 61 | upg_gio: gpio@f040a700 { | |
| 7c50181b GF |
62 | #gpio-cells = <2>; |
| 63 | #interrupt-cells = <2>; | |
| 5b7d414a GF |
64 | compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; |
| 65 | gpio-controller; | |
| 66 | interrupt-controller; | |
| 67 | reg = <0xf040a700 0x80>; | |
| 7c50181b GF |
68 | interrupt-parent = <&irq0_intc>; |
| 69 | interrupts = <0x6>; | |
| 70 | brcm,gpio-bank-widths = <32 32 32 24>; | |
| 71 | }; | |
| 72 | ||
| 73 | upg_gio_aon: gpio@f04172c0 { | |
| 74 | #gpio-cells = <2>; | |
| 75 | #interrupt-cells = <2>; | |
| 76 | compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; | |
| 77 | gpio-controller; | |
| 78 | interrupt-controller; | |
| 79 | reg = <0xf04172c0 0x40>; | |
| 80 | interrupt-parent = <&irq0_aon_intc>; | |
| 5b7d414a | 81 | interrupts = <0x6>; |
| 7c50181b GF |
82 | interrupts-extended = <&irq0_aon_intc 0x6>, |
| 83 | <&aon_pm_l2_intc 0x5>; | |
| 84 | wakeup-source; | |
| 85 | brcm,gpio-bank-widths = <18 4>; | |
| 5b7d414a | 86 | }; |