projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 89214f00 SA |
1 | BCM2835 Top-Level ("ARMCTRL") Interrupt Controller |
| 2 | ||
| 3 | The BCM2835 contains a custom top-level interrupt controller, which supports | |
| 4 | 72 interrupt sources using a 2-level register scheme. The interrupt | |
| 5 | controller, or the HW block containing it, is referred to occasionally | |
| 6 | as "armctrl" in the SoC documentation, hence naming of this binding. | |
| 7 | ||
| 8 | Required properties: | |
| 9 | ||
| 53f40352 | 10 | - compatible : should be "brcm,bcm2835-armctrl-ic" |
| 89214f00 SA |
11 | - reg : Specifies base physical address and size of the registers. |
| 12 | - interrupt-controller : Identifies the node as an interrupt controller | |
| 13 | - #interrupt-cells : Specifies the number of cells needed to encode an | |
| 14 | interrupt source. The value shall be 2. | |
| 15 | ||
| 16 | The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic | |
| 17 | pending" register, or 1/2 respectively for interrupts in the "IRQ pending | |
| 18 | 1/2" register. | |
| 19 | ||
| 20 | The 2nd cell contains the interrupt number within the bank. Valid values | |
| 21 | are 0..7 for bank 0, and 0..31 for bank 1. | |
| 22 | ||
| 23 | The interrupt sources are as follows: | |
| 24 | ||
| 25 | Bank 0: | |
| 26 | 0: ARM_TIMER | |
| 27 | 1: ARM_MAILBOX | |
| 28 | 2: ARM_DOORBELL_0 | |
| 29 | 3: ARM_DOORBELL_1 | |
| 30 | 4: VPU0_HALTED | |
| 31 | 5: VPU1_HALTED | |
| 32 | 6: ILLEGAL_TYPE0 | |
| 33 | 7: ILLEGAL_TYPE1 | |
| 34 | ||
| 35 | Bank 1: | |
| 36 | 0: TIMER0 | |
| 37 | 1: TIMER1 | |
| 38 | 2: TIMER2 | |
| 39 | 3: TIMER3 | |
| 40 | 4: CODEC0 | |
| 41 | 5: CODEC1 | |
| 42 | 6: CODEC2 | |
| 43 | 7: VC_JPEG | |
| 44 | 8: ISP | |
| 45 | 9: VC_USB | |
| 46 | 10: VC_3D | |
| 47 | 11: TRANSPOSER | |
| 48 | 12: MULTICORESYNC0 | |
| 49 | 13: MULTICORESYNC1 | |
| 50 | 14: MULTICORESYNC2 | |
| 51 | 15: MULTICORESYNC3 | |
| 52 | 16: DMA0 | |
| 53 | 17: DMA1 | |
| 54 | 18: VC_DMA2 | |
| 55 | 19: VC_DMA3 | |
| 56 | 20: DMA4 | |
| 57 | 21: DMA5 | |
| 58 | 22: DMA6 | |
| 59 | 23: DMA7 | |
| 60 | 24: DMA8 | |
| 61 | 25: DMA9 | |
| 62 | 26: DMA10 | |
| 63 | 27: DMA11 | |
| 64 | 28: DMA12 | |
| 65 | 29: AUX | |
| 66 | 30: ARM | |
| 67 | 31: VPUDMA | |
| 68 | ||
| 69 | Bank 2: | |
| 70 | 0: HOSTPORT | |
| 71 | 1: VIDEOSCALER | |
| 72 | 2: CCP2TX | |
| 73 | 3: SDC | |
| 74 | 4: DSI0 | |
| 75 | 5: AVE | |
| 76 | 6: CAM0 | |
| 77 | 7: CAM1 | |
| 78 | 8: HDMI0 | |
| 79 | 9: HDMI1 | |
| 80 | 10: PIXELVALVE1 | |
| 81 | 11: I2CSPISLV | |
| 82 | 12: DSI1 | |
| 83 | 13: PWA0 | |
| 84 | 14: PWA1 | |
| 85 | 15: CPR | |
| 86 | 16: SMI | |
| 87 | 17: GPIO0 | |
| 88 | 18: GPIO1 | |
| 89 | 19: GPIO2 | |
| 90 | 20: GPIO3 | |
| 91 | 21: VC_I2C | |
| 92 | 22: VC_SPI | |
| 93 | 23: VC_I2SPCM | |
| 94 | 24: VC_SDIO | |
| 95 | 25: VC_UART | |
| 96 | 26: SLIMBUS | |
| 97 | 27: VEC | |
| 98 | 28: CPG | |
| 99 | 29: RNG | |
| 100 | 30: VC_ARASANSDIO | |
| 101 | 31: AVSPMON | |
| 102 | ||
| 103 | Example: | |
| 104 | ||
| 105 | intc: interrupt-controller { | |
| 106 | compatible = "brcm,bcm2835-armctrl-ic"; | |
| 107 | reg = <0x7e00b200 0x200>; | |
| 108 | interrupt-controller; | |
| 109 | #interrupt-cells = <2>; | |
| 110 | }; |